diff options
| author | Eric Anholt <[email protected]> | 2017-07-27 12:05:56 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2017-10-10 10:45:22 -0700 |
| commit | ac0051a5075879970f12f614890c9c6d732663b6 (patch) | |
| tree | 39a723409f8052a04dce2a5b1d2c9bfac2ba6be7 /src/gallium/docs | |
| parent | 4aa700e0e09d694ecae60ee04b11ca6e7458afe7 (diff) | |
gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.
This commit introduces the core gallium support, vc4 changes will follow.
v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Drop vc4 changes from this commit, for clarity.
Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
Diffstat (limited to 'src/gallium/docs')
| -rw-r--r-- | src/gallium/docs/source/screen.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index b968b8c5733..bc0db429b38 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -408,6 +408,9 @@ The integer capabilities: with constant buffers. * ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as an address for indirect register indexing. +* ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports + GL_MESA_tile_raster_order, using the tile_raster_order_* fields in + pipe_rasterizer_state. .. _pipe_capf: |