diff options
author | Zack Rusin <[email protected]> | 2013-10-08 15:11:02 -0400 |
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committer | Zack Rusin <[email protected]> | 2013-10-09 18:30:20 -0400 |
commit | 6905698fc21710c18722295dedceb96ef5d5923b (patch) | |
tree | 448459df4604df868382f02fac033f354356f1c0 /src/gallium/docs | |
parent | c01c6a95b41607dc58a343b2aa67bc3da673ca35 (diff) |
gallium: Add support for 32x32 muls with 64 bit results
The code introduces two new 32bit integer multiplication opcodes which
can be used to produce correct 64 bit results. GLSL, OpenCL and D3D10+
require them. We use two seperate opcodes, because they match the
behavior of GLSL and OpenCL, are a lot easier to add than a single
opcode with multiple destinations and because there's not much (any)
difference wrt code-generation.
Signed-off-by: Zack Rusin <[email protected]>
Reviewed-by: José Fonseca <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
Diffstat (limited to 'src/gallium/docs')
-rw-r--r-- | src/gallium/docs/source/tgsi.rst | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 41f2798d704..f80c08d3175 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -1103,6 +1103,36 @@ Support for these opcodes indicated by PIPE_SHADER_CAP_INTEGERS (all of them?) dst.w = src0.w \times src1.w +.. opcode:: IMUL_HI - Signed Integer Multiply High Bits + + The high 32bits of the multiplication of 2 signed integers are returned. + +.. math:: + + dst.x = (src0.x \times src1.x) >> 32 + + dst.y = (src0.y \times src1.y) >> 32 + + dst.z = (src0.z \times src1.z) >> 32 + + dst.w = (src0.w \times src1.w) >> 32 + + +.. opcode:: UMUL_HI - Unsigned Integer Multiply High Bits + + The high 32bits of the multiplication of 2 unsigned integers are returned. + +.. math:: + + dst.x = (src0.x \times src1.x) >> 32 + + dst.y = (src0.y \times src1.y) >> 32 + + dst.z = (src0.z \times src1.z) >> 32 + + dst.w = (src0.w \times src1.w) >> 32 + + .. opcode:: IDIV - Signed Integer Division TBD: behavior for division by zero. |