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| author | Samuel Pitoiset <[email protected]> | 2016-02-03 18:57:58 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2016-02-13 15:51:17 +0100 |
| commit | 5e09ac78e5c25972fecf02e10363052a7b90f79f (patch) | |
| tree | 05f6577059e5fd0197150cfee927c9eef31ee744 /src/gallium/docs | |
| parent | 43f4420fba1c9855c0f127143a4ed13b170ac49b (diff) | |
gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS
This cap indicates the supported representations of programs. It should
be a mask of pipe_shader_ir bits. It will allow to enable
ARB_compute_shader if the underlying driver supports TGSI.
Changes from v2:
- improve description of PIPE_SHADER_CAP_SUPPORTED_IRS
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/docs')
| -rw-r--r-- | src/gallium/docs/source/screen.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 3324bcca6f4..c28a84ad946 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -415,6 +415,8 @@ to be 0. (also used to implement atomic counters). Having this be non-0 also implies support for the ``LOAD``, ``STORE``, and ``ATOM*`` TGSI opcodes. +* ``PIPE_SHADER_CAP_SUPPORTED_IRS``: Supported representations of the + program. It should be a mask of ``pipe_shader_ir`` bits. .. _pipe_compute_cap: |