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authorMarek Olšák <[email protected]>2014-01-27 21:42:07 +0100
committerMarek Olšák <[email protected]>2014-02-25 16:05:41 +0100
commit5f61f052b5fd8e590eca652fdac381452eb9853d (patch)
tree1346f2035ad3eeebc482f4ea8a84a9179db198de /src/gallium/docs/source/context.rst
parentd26a065b7496ef69754fde6e4d0006ccb76f7f3a (diff)
gallium: add interface for persistent and coherent buffer mappings
Required for ARB_buffer_storage.
Diffstat (limited to 'src/gallium/docs/source/context.rst')
-rw-r--r--src/gallium/docs/source/context.rst22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/gallium/docs/source/context.rst b/src/gallium/docs/source/context.rst
index 1037162aefb..64df0acb645 100644
--- a/src/gallium/docs/source/context.rst
+++ b/src/gallium/docs/source/context.rst
@@ -520,6 +520,16 @@ invalidates all read caches of the currently-set samplers.
+.. _memory_barrier:
+
+memory_barrier
+%%%%%%%%%%%%%%%
+
+This function flushes caches according to which of the PIPE_BARRIER_* flags
+are set.
+
+
+
.. _pipe_transfer:
PIPE_TRANSFER
@@ -557,6 +567,18 @@ These flags control the behavior of a transfer object.
Written ranges will be notified later with :ref:`transfer_flush_region`.
Cannot be used with ``PIPE_TRANSFER_READ``.
+``PIPE_TRANSFER_PERSISTENT``
+ Allows the resource to be used for rendering while mapped.
+ PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
+ the resource.
+ If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
+ must be called to ensure the device can see what the CPU has written.
+
+``PIPE_TRANSFER_COHERENT``
+ If PERSISTENT is set, this ensures any writes done by the device are
+ immediately visible to the CPU and vice versa.
+ PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
+ the resource.
Compute kernel execution
^^^^^^^^^^^^^^^^^^^^^^^^