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authorMichal Krol <[email protected]>2008-07-20 21:28:28 +0200
committerMichal Krol <[email protected]>2008-07-20 21:28:28 +0200
commit25a7f422b4e307dce966220d47794fb056d04aac (patch)
treea485f839aa88003dc699a77334f8ba718bddf6fb /src/gallium/auxiliary/tgsi
parent73e1d0be756537376495547bc1e798805884b8ef (diff)
tgsi: Warn if an indirect register not ADDR[0].
Diffstat (limited to 'src/gallium/auxiliary/tgsi')
-rw-r--r--src/gallium/auxiliary/tgsi/util/tgsi_sanity.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/gallium/auxiliary/tgsi/util/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/util/tgsi_sanity.c
index f11de815b06..08f3995b13e 100644
--- a/src/gallium/auxiliary/tgsi/util/tgsi_sanity.c
+++ b/src/gallium/auxiliary/tgsi/util/tgsi_sanity.c
@@ -171,11 +171,14 @@ iter_instruction(
inst->FullSrcRegisters[i].SrcRegister.Index,
inst->FullSrcRegisters[i].SrcRegister.Indirect );
if (inst->FullSrcRegisters[i].SrcRegister.Indirect) {
- check_register_usage(
- ctx,
- inst->FullSrcRegisters[i].SrcRegisterInd.File,
- inst->FullSrcRegisters[i].SrcRegisterInd.Index,
- FALSE );
+ uint file;
+ int index;
+
+ file = inst->FullSrcRegisters[i].SrcRegisterInd.File;
+ index = inst->FullSrcRegisters[i].SrcRegisterInd.Index;
+ check_register_usage( ctx, file, index, FALSE );
+ if (file != TGSI_FILE_ADDRESS || index != 0)
+ report_warning( ctx, "Indirect register not ADDR[0]" );
}
}