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authorMichal Krol <[email protected]>2009-07-31 18:12:53 +0200
committerMichal Krol <[email protected]>2009-07-31 18:14:40 +0200
commitcb90c43676c258419e4b617c908570891d3674cb (patch)
treebb4c581e9f4969bfc4c7ac163e0b8f1eee845846 /src/gallium/auxiliary/tgsi/tgsi_sanity.c
parentdc516d6e2afe7f157dbe5aad1288e5624b27e093 (diff)
Rename TGSI LOOP instruction to better match theri usage.
The LOOP/ENDLOOP pair is renamed to BGNFOR/ENDFOR as its behaviour is similar to a C language for-loop. The BGNLOOP2/ENDLOOP2 pair is renamed to BGNLOOP/ENDLOOP as now there is no name collision.
Diffstat (limited to 'src/gallium/auxiliary/tgsi/tgsi_sanity.c')
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_sanity.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
index cb62a95fc0a..4fe8553c423 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_sanity.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
@@ -242,8 +242,8 @@ iter_instruction(
}
switch (inst->Instruction.Opcode) {
- case TGSI_OPCODE_LOOP:
- case TGSI_OPCODE_ENDLOOP:
+ case TGSI_OPCODE_BGNFOR:
+ case TGSI_OPCODE_ENDFOR:
if (inst->FullDstRegisters[0].DstRegister.File != TGSI_FILE_LOOP ||
inst->FullDstRegisters[0].DstRegister.Index != 0) {
report_error(ctx, "Destination register must be LOOP[0]");
@@ -252,7 +252,7 @@ iter_instruction(
}
switch (inst->Instruction.Opcode) {
- case TGSI_OPCODE_LOOP:
+ case TGSI_OPCODE_BGNFOR:
if (inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
report_error(ctx, "Source register file must be either CONST or IMM");