gallium/cell: Remove the driver.

Complicates Gallium3D development and doesn't seem to have active users.

Signed-off-by: Kai Wasserbäch <[email protected]>
Signed-off-by: José Fonseca <[email protected]>

2 files changed, 0 insertions, 1500 deletions

diff --git a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c b/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c
deleted file mode 100644
index 53a0e722cff..00000000000
--- a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c
+++ /dev/null
@@ -1,1067 +0,0 @@
-/*
- * (C) Copyright IBM Corporation 2008
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
- * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/**
- * \file
- * Real-time assembly generation interface for Cell B.E. SPEs.
- *
- * \author Ian Romanick <[email protected]>
- * \author Brian Paul
- */
-
-
-#include <stdio.h>
-#include "pipe/p_compiler.h"
-#include "util/u_memory.h"
-#include "rtasm_ppc_spe.h"
-
-
-#ifdef GALLIUM_CELL
-/**
- * SPE instruction types
- *
- * There are 6 primary instruction encodings used on the Cell's SPEs.  Each of
- * the following unions encodes one type.
- *
- * \bug
- * If, at some point, we start generating SPE code from a little-endian host
- * these unions will not work.
- */
-/*@{*/
-/**
- * Encode one output register with two input registers
- */
-union spe_inst_RR {
-    uint32_t bits;
-    struct {
-	unsigned op:11;
-	unsigned rB:7;
-	unsigned rA:7;
-	unsigned rT:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with three input registers
- */
-union spe_inst_RRR {
-    uint32_t bits;
-    struct {
-	unsigned op:4;
-	unsigned rT:7;
-	unsigned rB:7;
-	unsigned rA:7;
-	unsigned rC:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with one input reg. and a 7-bit signed immed
- */
-union spe_inst_RI7 {
-    uint32_t bits;
-    struct {
-	unsigned op:11;
-	unsigned i7:7;
-	unsigned rA:7;
-	unsigned rT:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with one input reg. and an 8-bit signed immed
- */
-union spe_inst_RI8 {
-    uint32_t bits;
-    struct {
-	unsigned op:10;
-	unsigned i8:8;
-	unsigned rA:7;
-	unsigned rT:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with one input reg. and a 10-bit signed immed
- */
-union spe_inst_RI10 {
-    uint32_t bits;
-    struct {
-	unsigned op:8;
-	unsigned i10:10;
-	unsigned rA:7;
-	unsigned rT:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with a 16-bit signed immediate
- */
-union spe_inst_RI16 {
-    uint32_t bits;
-    struct {
-	unsigned op:9;
-	unsigned i16:16;
-	unsigned rT:7;
-    } inst;
-};
-
-
-/**
- * Encode one output register with a 18-bit signed immediate
- */
-union spe_inst_RI18 {
-    uint32_t bits;
-    struct {
-	unsigned op:7;
-	unsigned i18:18;
-	unsigned rT:7;
-    } inst;
-};
-/*@}*/
-
-
-static void
-indent(const struct spe_function *p)
-{
-   int i;
-   for (i = 0; i < p->indent; i++) {
-      putchar(' ');
-   }
-}
-
-
-static const char *
-rem_prefix(const char *longname)
-{
-   return longname + 4;
-}
-
-
-static const char *
-reg_name(int reg)
-{
-   switch (reg) {
-   case SPE_REG_SP:
-      return "$sp";
-   case SPE_REG_RA:
-      return "$lr";
-   default:
-      {
-         /* cycle through four buffers to handle multiple calls per printf */
-         static char buf[4][10];
-         static int b = 0;
-         b = (b + 1) % 4;
-         sprintf(buf[b], "$%d", reg);
-         return buf[b];
-      }
-   }
-}
-
-
-static void
-emit_instruction(struct spe_function *p, uint32_t inst_bits)
-{
-   if (!p->store)
-      return;  /* out of memory, drop the instruction */
-
-   if (p->num_inst == p->max_inst) {
-      /* allocate larger buffer */
-      uint32_t *newbuf;
-      p->max_inst *= 2;  /* 2x larger */
-      newbuf = align_malloc(p->max_inst * SPE_INST_SIZE, 16);
-      if (newbuf) {
-         memcpy(newbuf, p->store, p->num_inst * SPE_INST_SIZE);
-      }
-      align_free(p->store);
-      p->store = newbuf;
-      if (!p->store) {
-         /* out of memory */
-         p->num_inst = 0;
-         return;
-      }
-   }
-
-   p->store[p->num_inst++] = inst_bits;
-}
-
-
-
-static void emit_RR(struct spe_function *p, unsigned op, int rT,
-		    int rA, int rB, const char *name)
-{
-    union spe_inst_RR inst;
-    inst.inst.op = op;
-    inst.inst.rB = rB;
-    inst.inst.rA = rA;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, %s, %s\n",
-              rem_prefix(name), reg_name(rT), reg_name(rA), reg_name(rB));
-    }
-}
-
-
-static void emit_RRR(struct spe_function *p, unsigned op, int rT,
-                     int rA, int rB, int rC, const char *name)
-{
-    union spe_inst_RRR inst;
-    inst.inst.op = op;
-    inst.inst.rT = rT;
-    inst.inst.rB = rB;
-    inst.inst.rA = rA;
-    inst.inst.rC = rC;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, %s, %s, %s\n", rem_prefix(name), reg_name(rT),
-              reg_name(rA), reg_name(rB), reg_name(rC));
-    }
-}
-
-
-static void emit_RI7(struct spe_function *p, unsigned op, int rT,
-		     int rA, int imm, const char *name)
-{
-    union spe_inst_RI7 inst;
-    inst.inst.op = op;
-    inst.inst.i7 = imm;
-    inst.inst.rA = rA;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, %s, 0x%x\n",
-              rem_prefix(name), reg_name(rT), reg_name(rA), imm);
-    }
-}
-
-
-
-static void emit_RI8(struct spe_function *p, unsigned op, int rT,
-		     int rA, int imm, const char *name)
-{
-    union spe_inst_RI8 inst;
-    inst.inst.op = op;
-    inst.inst.i8 = imm;
-    inst.inst.rA = rA;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, %s, 0x%x\n",
-              rem_prefix(name), reg_name(rT), reg_name(rA), imm);
-    }
-}
-
-
-
-static void emit_RI10(struct spe_function *p, unsigned op, int rT,
-		      int rA, int imm, const char *name)
-{
-    union spe_inst_RI10 inst;
-    inst.inst.op = op;
-    inst.inst.i10 = imm;
-    inst.inst.rA = rA;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, %s, 0x%x\n",
-              rem_prefix(name), reg_name(rT), reg_name(rA), imm);
-    }
-}
-
-
-/** As above, but do range checking on signed immediate value */
-static void emit_RI10s(struct spe_function *p, unsigned op, int rT,
-                       int rA, int imm, const char *name)
-{
-    assert(imm <= 511);
-    assert(imm >= -512);
-    emit_RI10(p, op, rT, rA, imm, name);
-}
-
-
-static void emit_RI16(struct spe_function *p, unsigned op, int rT,
-		      int imm, const char *name)
-{
-    union spe_inst_RI16 inst;
-    inst.inst.op = op;
-    inst.inst.i16 = imm;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
-    }
-}
-
-
-static void emit_RI18(struct spe_function *p, unsigned op, int rT,
-		      int imm, const char *name)
-{
-    union spe_inst_RI18 inst;
-    inst.inst.op = op;
-    inst.inst.i18 = imm;
-    inst.inst.rT = rT;
-    emit_instruction(p, inst.bits);
-    if (p->print) {
-       indent(p);
-       printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
-    }
-}
-
-
-#define EMIT(_name, _op) \
-void _name (struct spe_function *p) \
-{ \
-   emit_RR(p, _op, 0, 0, 0, __FUNCTION__); \
-}
-
-#define EMIT_(_name, _op) \
-void _name (struct spe_function *p, int rT) \
-{ \
-   emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
-}
-
-#define EMIT_R(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA) \
-{ \
-   emit_RR(p, _op, rT, rA, 0, __FUNCTION__);                 \
-}
-
-#define EMIT_RR(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA, int rB) \
-{ \
-   emit_RR(p, _op, rT, rA, rB, __FUNCTION__);                \
-}
-
-#define EMIT_RRR(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA, int rB, int rC) \
-{ \
-   emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__);           \
-}
-
-#define EMIT_RI7(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA, int imm) \
-{ \
-   emit_RI7(p, _op, rT, rA, imm, __FUNCTION__);              \
-}
-
-#define EMIT_RI8(_name, _op, bias) \
-void _name (struct spe_function *p, int rT, int rA, int imm) \
-{ \
-   emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__);       \
-}
-
-#define EMIT_RI10(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA, int imm) \
-{ \
-   emit_RI10(p, _op, rT, rA, imm, __FUNCTION__);             \
-}
-
-#define EMIT_RI10s(_name, _op) \
-void _name (struct spe_function *p, int rT, int rA, int imm) \
-{ \
-   emit_RI10s(p, _op, rT, rA, imm, __FUNCTION__);             \
-}
-
-#define EMIT_RI16(_name, _op) \
-void _name (struct spe_function *p, int rT, int imm) \
-{ \
-   emit_RI16(p, _op, rT, imm, __FUNCTION__);                 \
-}
-
-#define EMIT_RI18(_name, _op) \
-void _name (struct spe_function *p, int rT, int imm) \
-{ \
-   emit_RI18(p, _op, rT, imm, __FUNCTION__);                 \
-}
-
-#define EMIT_I16(_name, _op) \
-void _name (struct spe_function *p, int imm) \
-{ \
-   emit_RI16(p, _op, 0, imm, __FUNCTION__);                  \
-}
-
-#include "rtasm_ppc_spe.h"
-
-
-
-/**
- * Initialize an spe_function.
- * \param code_size  initial size of instruction buffer to allocate, in bytes.
- *                   If zero, use a default.
- */
-void spe_init_func(struct spe_function *p, unsigned code_size)
-{
-    uint i;
-
-    if (!code_size)
-       code_size = 64;
-
-    p->num_inst = 0;
-    p->max_inst = code_size / SPE_INST_SIZE;
-    p->store = align_malloc(code_size, 16);
-
-    p->set_count = 0;
-    memset(p->regs, 0, SPE_NUM_REGS * sizeof(p->regs[0]));
-
-    /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
-     */
-    p->regs[0] = p->regs[1] = p->regs[2] = 1;
-    for (i = 80; i <= 127; i++) {
-      p->regs[i] = 1;
-    }
-
-    p->print = FALSE;
-    p->indent = 0;
-}
-
-
-void spe_release_func(struct spe_function *p)
-{
-    assert(p->num_inst <= p->max_inst);
-    if (p->store != NULL) {
-        align_free(p->store);
-    }
-    p->store = NULL;
-}
-
-
-/** Return current code size in bytes. */
-unsigned spe_code_size(const struct spe_function *p)
-{
-   return p->num_inst * SPE_INST_SIZE;
-}
-
-
-/**
- * Allocate a SPE register.
- * \return register index or -1 if none left.
- */
-int spe_allocate_available_register(struct spe_function *p)
-{
-   unsigned i;
-   for (i = 0; i < SPE_NUM_REGS; i++) {
-      if (p->regs[i] == 0) {
-         p->regs[i] = 1;
-         return i;
-      }
-   }
-
-   return -1;
-}
-
-
-/**
- * Mark the given SPE register as "allocated".
- */
-int spe_allocate_register(struct spe_function *p, int reg)
-{
-   assert(reg < SPE_NUM_REGS);
-   assert(p->regs[reg] == 0);
-   p->regs[reg] = 1;
-   return reg;
-}
-
-
-/**
- * Mark the given SPE register as "unallocated".  Note that this should
- * only be used on registers allocated in the current register set; an
- * assertion will fail if an attempt is made to deallocate a register
- * allocated in an earlier register set.
- */
-void spe_release_register(struct spe_function *p, int reg)
-{
-   assert(reg >= 0);
-   assert(reg < SPE_NUM_REGS);
-   assert(p->regs[reg] == 1);
-
-   p->regs[reg] = 0;
-}
-
-/**
- * Start a new set of registers.  This can be called if
- * it will be difficult later to determine exactly what
- * registers were actually allocated during a code generation
- * sequence, and you really just want to deallocate all of them.
- */
-void spe_allocate_register_set(struct spe_function *p)
-{
-   uint i;
-
-   /* Keep track of the set count.  If it ever wraps around to 0, 
-    * we're in trouble.
-    */
-   p->set_count++;
-   assert(p->set_count > 0);
-
-   /* Increment the allocation count of all registers currently
-    * allocated.  Then any registers that are allocated in this set
-    * will be the only ones with a count of 1; they'll all be released
-    * when the register set is released.
-    */
-   for (i = 0; i < SPE_NUM_REGS; i++) {
-      if (p->regs[i] > 0)
-         p->regs[i]++;
-   }
-}
-
-void spe_release_register_set(struct spe_function *p)
-{
-   uint i;
-
-   /* If the set count drops below zero, we're in trouble. */
-   assert(p->set_count > 0);
-   p->set_count--;
-
-   /* Drop the allocation level of all registers.  Any allocated
-    * during this register set will drop to 0 and then become
-    * available.
-    */
-   for (i = 0; i < SPE_NUM_REGS; i++) {
-      if (p->regs[i] > 0)
-         p->regs[i]--;
-   }
-}
-
-
-unsigned
-spe_get_registers_used(const struct spe_function *p, ubyte used[])
-{
-   unsigned i, num = 0;
-   /* only count registers in the range available to callers */
-   for (i = 2; i < 80; i++) {
-      if (p->regs[i]) {
-         used[num++] = i;
-      }
-   }
-   return num;
-}
-
-
-void
-spe_print_code(struct spe_function *p, boolean enable)
-{
-   p->print = enable;
-}
-
-
-void
-spe_indent(struct spe_function *p, int spaces)
-{
-   p->indent += spaces;
-}
-
-
-void
-spe_comment(struct spe_function *p, int rel_indent, const char *s)
-{
-   if (p->print) {
-      p->indent += rel_indent;
-      indent(p);
-      p->indent -= rel_indent;
-      printf("# %s\n", s);
-   }
-}
-
-
-/**
- * Load quad word.
- * NOTE: offset is in bytes and the least significant 4 bits must be zero!
- */
-void spe_lqd(struct spe_function *p, int rT, int rA, int offset)
-{
-   const boolean pSave = p->print;
-
-   /* offset must be a multiple of 16 */
-   assert(offset % 16 == 0);
-   /* offset must fit in 10-bit signed int field, after shifting */
-   assert((offset >> 4) <= 511);
-   assert((offset >> 4) >= -512);
-
-   p->print = FALSE;
-   emit_RI10(p, 0x034, rT, rA, offset >> 4, "spe_lqd");
-   p->print = pSave;
-
-   if (p->print) {
-      indent(p);
-      printf("lqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
-   }
-}
-
-
-/**
- * Store quad word.
- * NOTE: offset is in bytes and the least significant 4 bits must be zero!
- */
-void spe_stqd(struct spe_function *p, int rT, int rA, int offset)
-{
-   const boolean pSave = p->print;
-
-   /* offset must be a multiple of 16 */
-   assert(offset % 16 == 0);
-   /* offset must fit in 10-bit signed int field, after shifting */
-   assert((offset >> 4) <= 511);
-   assert((offset >> 4) >= -512);
-
-   p->print = FALSE;
-   emit_RI10(p, 0x024, rT, rA, offset >> 4, "spe_stqd");
-   p->print = pSave;
-
-   if (p->print) {
-      indent(p);
-      printf("stqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
-   }
-}
-
-
-/**
- * For branch instructions:
- * \param d  if 1, disable interupts if branch is taken
- * \param e  if 1, enable interupts if branch is taken
- * If d and e are both zero, don't change interupt status (right?)
- */
-
-/** Branch Indirect to address in rA */
-void spe_bi(struct spe_function *p, int rA, int d, int e)
-{
-   emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Interupt Return */
-void spe_iret(struct spe_function *p, int rA, int d, int e)
-{
-   emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect and set link on external data */
-void spe_bisled(struct spe_function *p, int rT, int rA, int d,
-		int e)
-{
-   emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect and set link.  Save PC in rT, jump to rA. */
-void spe_bisl(struct spe_function *p, int rT, int rA, int d,
-		int e)
-{
-   emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect if zero word.  If rT.word[0]==0, jump to rA. */
-void spe_biz(struct spe_function *p, int rT, int rA, int d, int e)
-{
-   emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect if non-zero word.  If rT.word[0]!=0, jump to rA. */
-void spe_binz(struct spe_function *p, int rT, int rA, int d, int e)
-{
-   emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect if zero halfword.  If rT.halfword[1]==0, jump to rA. */
-void spe_bihz(struct spe_function *p, int rT, int rA, int d, int e)
-{
-   emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-/** Branch indirect if non-zero halfword.  If rT.halfword[1]!=0, jump to rA. */
-void spe_bihnz(struct spe_function *p, int rT, int rA, int d, int e)
-{
-   emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
-}
-
-
-/* Hint-for-branch instructions
- */
-#if 0
-hbr;
-hbra;
-hbrr;
-#endif
-
-
-/* Control instructions
- */
-#if 0
-stop;
-EMIT_RR  (spe_stopd, 0x140);
-EMIT_    (spe_nop,   0x201);
-sync;
-EMIT_    (spe_dsync, 0x003);
-EMIT_R   (spe_mfspr, 0x00c);
-EMIT_R   (spe_mtspr, 0x10c);
-#endif
-
-
-/**
- ** Helper / "macro" instructions.
- ** Use somewhat verbose names as a reminder that these aren't native
- ** SPE instructions.
- **/
-
-
-void
-spe_load_float(struct spe_function *p, int rT, float x)
-{
-   if (x == 0.0f) {
-      spe_il(p, rT, 0x0);
-   }
-   else if (x == 0.5f) {
-      spe_ilhu(p, rT, 0x3f00);
-   }
-   else if (x == 1.0f) {
-      spe_ilhu(p, rT, 0x3f80);
-   }
-   else if (x == -1.0f) {
-      spe_ilhu(p, rT, 0xbf80);
-   }
-   else {
-      union {
-         float f;
-         unsigned u;
-      } bits;
-      bits.f = x;
-      spe_ilhu(p, rT, bits.u >> 16);
-      spe_iohl(p, rT, bits.u & 0xffff);
-   }
-}
-
-
-void
-spe_load_int(struct spe_function *p, int rT, int i)
-{
-   if (-32768 <= i && i <= 32767) {
-      spe_il(p, rT, i);
-   }
-   else {
-      spe_ilhu(p, rT, i >> 16);
-      if (i & 0xffff)
-         spe_iohl(p, rT, i & 0xffff);
-   }
-}
-
-void spe_load_uint(struct spe_function *p, int rT, uint ui)
-{
-   /* If the whole value is in the lower 18 bits, use ila, which
-    * doesn't sign-extend.  Otherwise, if the two halfwords of
-    * the constant are identical, use ilh.  Otherwise, if every byte of
-    * the desired value is 0x00 or 0xff, we can use Form Select Mask for
-    * Bytes Immediate (fsmbi) to load the value in a single instruction.
-    * Otherwise, in the general case, we have to use ilhu followed by iohl.
-    */
-   if ((ui & 0x0003ffff) == ui) {
-      spe_ila(p, rT, ui);
-   }
-   else if ((ui >> 16) == (ui & 0xffff)) {
-      spe_ilh(p, rT, ui & 0xffff);
-   }
-   else if (
-      ((ui & 0x000000ff) == 0 || (ui & 0x000000ff) == 0x000000ff) &&
-      ((ui & 0x0000ff00) == 0 || (ui & 0x0000ff00) == 0x0000ff00) &&
-      ((ui & 0x00ff0000) == 0 || (ui & 0x00ff0000) == 0x00ff0000) &&
-      ((ui & 0xff000000) == 0 || (ui & 0xff000000) == 0xff000000)
-   ) {
-      uint mask = 0;
-      /* fsmbi duplicates each bit in the given mask eight times,
-       * using a 16-bit value to initialize a 16-byte quadword.
-       * Each 4-bit nybble of the mask corresponds to a full word
-       * of the result; look at the value and figure out the mask
-       * (replicated for each word in the quadword), and then
-       * form the "select mask" to get the value.
-       */
-      if ((ui & 0x000000ff) == 0x000000ff) mask |= 0x1111;
-      if ((ui & 0x0000ff00) == 0x0000ff00) mask |= 0x2222;
-      if ((ui & 0x00ff0000) == 0x00ff0000) mask |= 0x4444;
-      if ((ui & 0xff000000) == 0xff000000) mask |= 0x8888;
-      spe_fsmbi(p, rT, mask);
-   }
-   else {
-      /* The general case: this usually uses two instructions, but
-       * may use only one if the low-order 16 bits of each word are 0.
-       */
-      spe_ilhu(p, rT, ui >> 16);
-      if (ui & 0xffff)
-         spe_iohl(p, rT, ui & 0xffff);
-   }
-}
-
-/**
- * This function is constructed identically to spe_xor_uint() below.
- * Changes to one should be made in the other.
- */
-void
-spe_and_uint(struct spe_function *p, int rT, int rA, uint ui)
-{
-   /* If we can, emit a single instruction, either And Byte Immediate
-    * (which uses the same constant across each byte), And Halfword Immediate
-    * (which sign-extends a 10-bit immediate to 16 bits and uses that
-    * across each halfword), or And Word Immediate (which sign-extends
-    * a 10-bit immediate to 32 bits).
-    *
-    * Otherwise, we'll need to use a temporary register.
-    */
-   uint tmp;
-
-   /* If the upper 23 bits are all 0s or all 1s, sign extension
-    * will work and we can use And Word Immediate
-    */
-   tmp = ui & 0xfffffe00;
-   if (tmp == 0xfffffe00 || tmp  == 0) {
-      spe_andi(p, rT, rA, ui & 0x000003ff);
-      return;
-   }
-   
-   /* If the ui field is symmetric along halfword boundaries and
-    * the upper 7 bits of each halfword are all 0s or 1s, we
-    * can use And Halfword Immediate
-    */
-   tmp = ui & 0xfe00fe00;
-   if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
-      spe_andhi(p, rT, rA, ui & 0x000003ff);
-      return;
-   }
-
-   /* If the ui field is symmetric in each byte, then we can use
-    * the And Byte Immediate instruction.
-    */
-   tmp = ui & 0x000000ff;
-   if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
-      spe_andbi(p, rT, rA, tmp);
-      return;
-   }
-
-   /* Otherwise, we'll have to use a temporary register. */
-   int tmp_reg = spe_allocate_available_register(p);
-   spe_load_uint(p, tmp_reg, ui);
-   spe_and(p, rT, rA, tmp_reg);
-   spe_release_register(p, tmp_reg);
-}
-
-
-/**
- * This function is constructed identically to spe_and_uint() above.
- * Changes to one should be made in the other.
- */
-void
-spe_xor_uint(struct spe_function *p, int rT, int rA, uint ui)
-{
-   /* If we can, emit a single instruction, either Exclusive Or Byte 
-    * Immediate (which uses the same constant across each byte), Exclusive 
-    * Or Halfword Immediate (which sign-extends a 10-bit immediate to 
-    * 16 bits and uses that across each halfword), or Exclusive Or Word 
-    * Immediate (which sign-extends a 10-bit immediate to 32 bits).
-    *
-    * Otherwise, we'll need to use a temporary register.
-    */
-   uint tmp;
-
-   /* If the upper 23 bits are all 0s or all 1s, sign extension
-    * will work and we can use Exclusive Or Word Immediate
-    */
-   tmp = ui & 0xfffffe00;
-   if (tmp == 0xfffffe00 || tmp  == 0) {
-      spe_xori(p, rT, rA, ui & 0x000003ff);
-      return;
-   }
-   
-   /* If the ui field is symmetric along halfword boundaries and
-    * the upper 7 bits of each halfword are all 0s or 1s, we
-    * can use Exclusive Or Halfword Immediate
-    */
-   tmp = ui & 0xfe00fe00;
-   if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
-      spe_xorhi(p, rT, rA, ui & 0x000003ff);
-      return;
-   }
-
-   /* If the ui field is symmetric in each byte, then we can use
-    * the Exclusive Or Byte Immediate instruction.
-    */
-   tmp = ui & 0x000000ff;
-   if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
-      spe_xorbi(p, rT, rA, tmp);
-      return;
-   }
-
-   /* Otherwise, we'll have to use a temporary register. */
-   int tmp_reg = spe_allocate_available_register(p);
-   spe_load_uint(p, tmp_reg, ui);
-   spe_xor(p, rT, rA, tmp_reg);
-   spe_release_register(p, tmp_reg);
-}
-
-void
-spe_compare_equal_uint(struct spe_function *p, int rT, int rA, uint ui)
-{
-   /* If the comparison value is 9 bits or less, it fits inside a
-    * Compare Equal Word Immediate instruction.
-    */
-   if ((ui & 0x000001ff) == ui) {
-      spe_ceqi(p, rT, rA, ui);
-   }
-   /* Otherwise, we're going to have to load a word first. */
-   else {
-      int tmp_reg = spe_allocate_available_register(p);
-      spe_load_uint(p, tmp_reg, ui);
-      spe_ceq(p, rT, rA, tmp_reg);
-      spe_release_register(p, tmp_reg);
-   }
-}
-
-void
-spe_compare_greater_uint(struct spe_function *p, int rT, int rA, uint ui)
-{
-   /* If the comparison value is 10 bits or less, it fits inside a
-    * Compare Logical Greater Than Word Immediate instruction.
-    */
-   if ((ui & 0x000003ff) == ui) {
-      spe_clgti(p, rT, rA, ui);
-   }
-   /* Otherwise, we're going to have to load a word first. */
-   else {
-      int tmp_reg = spe_allocate_available_register(p);
-      spe_load_uint(p, tmp_reg, ui);
-      spe_clgt(p, rT, rA, tmp_reg);
-      spe_release_register(p, tmp_reg);
-   }
-}
-
-void
-spe_splat(struct spe_function *p, int rT, int rA)
-{
-   /* Use a temporary, just in case rT == rA */
-   int tmp_reg = spe_allocate_available_register(p);
-   /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
-   spe_ila(p, tmp_reg, 0x00010203);
-   spe_shufb(p, rT, rA, rA, tmp_reg);
-   spe_release_register(p, tmp_reg);
-}
-
-
-void
-spe_complement(struct spe_function *p, int rT, int rA)
-{
-   spe_nor(p, rT, rA, rA);
-}
-
-
-void
-spe_move(struct spe_function *p, int rT, int rA)
-{
-   /* Use different instructions depending on the instruction address
-    * to take advantage of the dual pipelines.
-    */
-   if (p->num_inst & 1)
-      spe_shlqbyi(p, rT, rA, 0);  /* odd pipe */
-   else
-      spe_ori(p, rT, rA, 0);  /* even pipe */
-}
-
-
-void
-spe_zero(struct spe_function *p, int rT)
-{
-   spe_xor(p, rT, rT, rT);
-}
-
-
-void
-spe_splat_word(struct spe_function *p, int rT, int rA, int word)
-{
-   assert(word >= 0);
-   assert(word <= 3);
-
-   if (word == 0) {
-      int tmp1 = rT;
-      spe_ila(p, tmp1, 66051);
-      spe_shufb(p, rT, rA, rA, tmp1);
-   }
-   else {
-      /* XXX review this, we may not need the rotqbyi instruction */
-      int tmp1 = rT;
-      int tmp2 = spe_allocate_available_register(p);
-
-      spe_ila(p, tmp1, 66051);
-      spe_rotqbyi(p, tmp2, rA, 4 * word);
-      spe_shufb(p, rT, tmp2, tmp2, tmp1);
-
-      spe_release_register(p, tmp2);
-   }
-}
-
-/**
- * For each 32-bit float element of rA and rB, choose the smaller of the
- * two, compositing them into the rT register.
- * 
- * The Float Compare Greater Than (fcgt) instruction will put 1s into
- * compare_reg where rA > rB, and 0s where rA <= rB.
- *
- * Then the Select Bits (selb) instruction will take bits from rA where
- * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
- * where rA <= rB and from rB where rB > rA, which is exactly the
- * "min" operation.
- *
- * The compare_reg could in many cases be the same as rT, unless
- * rT == rA || rt == rB.  But since this is common in constructions
- * like "x = min(x, a)", we always allocate a new register to be safe.
- */
-void 
-spe_float_min(struct spe_function *p, int rT, int rA, int rB)
-{
-   int compare_reg = spe_allocate_available_register(p);
-   spe_fcgt(p, compare_reg, rA, rB);
-   spe_selb(p, rT, rA, rB, compare_reg);
-   spe_release_register(p, compare_reg);
-}
-
-/**
- * For each 32-bit float element of rA and rB, choose the greater of the
- * two, compositing them into the rT register.
- * 
- * The logic is similar to that of spe_float_min() above; the only
- * difference is that the registers on spe_selb() have been reversed,
- * so that the larger of the two is selected instead of the smaller.
- */
-void 
-spe_float_max(struct spe_function *p, int rT, int rA, int rB)
-{
-   int compare_reg = spe_allocate_available_register(p);
-   spe_fcgt(p, compare_reg, rA, rB);
-   spe_selb(p, rT, rB, rA, compare_reg);
-   spe_release_register(p, compare_reg);
-}
-
-#endif /* GALLIUM_CELL */
diff --git a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h b/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h
deleted file mode 100644
index 65d9c774154..00000000000
--- a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright IBM Corporation 2008
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
- * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/**
- * \file
- * Real-time assembly generation interface for Cell B.E. SPEs.
- * For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf
- *
- * \author Ian Romanick <[email protected]>
- * \author Brian Paul
- */
-
-#ifndef RTASM_PPC_SPE_H
-#define RTASM_PPC_SPE_H
-
-/** 4 bytes per instruction */
-#define SPE_INST_SIZE 4
-
-/** number of general-purpose SIMD registers */
-#define SPE_NUM_REGS  128
-
-/** Return Address register (aka $lr / Link Register) */
-#define SPE_REG_RA  0
-
-/** Stack Pointer register (aka $sp) */
-#define SPE_REG_SP  1
-
-
-struct spe_function
-{
-   uint32_t *store;  /**< instruction buffer */
-   uint num_inst;
-   uint max_inst;
-
-   /**
-    * The "set count" reflects the number of nested register sets
-    * are allowed.  In the unlikely case that we exceed the set count,
-    * register allocation will start to be confused, which is critical
-    * enough that we check for it.
-    */
-   unsigned char set_count;
-
-   /** 
-    * Flags for used and unused registers.  Each byte corresponds to a
-    * register; a 0 in that byte means that the register is available.
-    * A value of 1 means that the register was allocated in the current
-    * register set.  Any other value N means that the register was allocated
-    * N register sets ago.
-     *
-     * \sa
-     * spe_allocate_register, spe_allocate_available_register,
-     * spe_allocate_register_set, spe_release_register_set, spe_release_register, 
-     */
-    unsigned char regs[SPE_NUM_REGS];
-
-    boolean print; /**< print/dump instructions as they're emitted? */
-    int indent;    /**< number of spaces to indent */
-};
-
-
-extern void spe_init_func(struct spe_function *p, uint code_size);
-extern void spe_release_func(struct spe_function *p);
-extern uint spe_code_size(const struct spe_function *p);
-
-extern int spe_allocate_available_register(struct spe_function *p);
-extern int spe_allocate_register(struct spe_function *p, int reg);
-extern void spe_release_register(struct spe_function *p, int reg);
-extern void spe_allocate_register_set(struct spe_function *p);
-extern void spe_release_register_set(struct spe_function *p);
-
-extern uint spe_get_registers_used(const struct spe_function *p, ubyte used[]);
-
-extern void spe_print_code(struct spe_function *p, boolean enable);
-extern void spe_indent(struct spe_function *p, int spaces);
-extern void spe_comment(struct spe_function *p, int rel_indent, const char *s);
-
-
-#endif /* RTASM_PPC_SPE_H */
-
-#ifndef EMIT
-#define EMIT(_name, _op) \
-    extern void _name (struct spe_function *p);
-#define EMIT_(_name, _op) \
-    extern void _name (struct spe_function *p, int rT);
-#define EMIT_R(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA);
-#define EMIT_RR(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA, int rB);
-#define EMIT_RRR(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA, int rB, int rC);
-#define EMIT_RI7(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA, int imm);
-#define EMIT_RI8(_name, _op, bias) \
-    extern void _name (struct spe_function *p, int rT, int rA, int imm);
-#define EMIT_RI10(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA, int imm);
-#define EMIT_RI10s(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int rA, int imm);
-#define EMIT_RI16(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int imm);
-#define EMIT_RI18(_name, _op) \
-    extern void _name (struct spe_function *p, int rT, int imm);
-#define EMIT_I16(_name, _op) \
-    extern void _name (struct spe_function *p, int imm);
-#define UNDEF_EMIT_MACROS
-#endif /* EMIT */
-
-
-/* Memory load / store instructions
- */
-EMIT_RR  (spe_lqx,  0x1c4)
-EMIT_RI16(spe_lqa,  0x061)
-EMIT_RI16(spe_lqr,  0x067)
-EMIT_RR  (spe_stqx, 0x144)
-EMIT_RI16(spe_stqa, 0x041)
-EMIT_RI16(spe_stqr, 0x047)
-EMIT_RI7 (spe_cbd,  0x1f4)
-EMIT_RR  (spe_cbx,  0x1d4)
-EMIT_RI7 (spe_chd,  0x1f5)
-EMIT_RI7 (spe_chx,  0x1d5)
-EMIT_RI7 (spe_cwd,  0x1f6)
-EMIT_RI7 (spe_cwx,  0x1d6)
-EMIT_RI7 (spe_cdd,  0x1f7)
-EMIT_RI7 (spe_cdx,  0x1d7)
-
-
-/* Constant formation instructions
- */
-EMIT_RI16(spe_ilh,   0x083)
-EMIT_RI16(spe_ilhu,  0x082)
-EMIT_RI16(spe_il,    0x081)
-EMIT_RI18(spe_ila,   0x021)
-EMIT_RI16(spe_iohl,  0x0c1)
-EMIT_RI16(spe_fsmbi, 0x065)
-
-
-
-/* Integer and logical instructions
- */
-EMIT_RR  (spe_ah,      0x0c8)
-EMIT_RI10(spe_ahi,     0x01d)
-EMIT_RR  (spe_a,       0x0c0)
-EMIT_RI10s(spe_ai,      0x01c)
-EMIT_RR  (spe_sfh,     0x048)
-EMIT_RI10(spe_sfhi,    0x00d)
-EMIT_RR  (spe_sf,      0x040)
-EMIT_RI10(spe_sfi,     0x00c)
-EMIT_RR  (spe_addx,    0x340)
-EMIT_RR  (spe_cg,      0x0c2)
-EMIT_RR  (spe_cgx,     0x342)
-EMIT_RR  (spe_sfx,     0x341)
-EMIT_RR  (spe_bg,      0x042)
-EMIT_RR  (spe_bgx,     0x343)
-EMIT_RR  (spe_mpy,     0x3c4)
-EMIT_RR  (spe_mpyu,    0x3cc)
-EMIT_RI10(spe_mpyi,    0x074)
-EMIT_RI10(spe_mpyui,   0x075)
-EMIT_RRR (spe_mpya,    0x00c)
-EMIT_RR  (spe_mpyh,    0x3c5)
-EMIT_RR  (spe_mpys,    0x3c7)
-EMIT_RR  (spe_mpyhh,   0x3c6)
-EMIT_RR  (spe_mpyhha,  0x346)
-EMIT_RR  (spe_mpyhhu,  0x3ce)
-EMIT_RR  (spe_mpyhhau, 0x34e)
-EMIT_R   (spe_clz,     0x2a5)
-EMIT_R   (spe_cntb,    0x2b4)
-EMIT_R   (spe_fsmb,    0x1b6)
-EMIT_R   (spe_fsmh,    0x1b5)
-EMIT_R   (spe_fsm,     0x1b4)
-EMIT_R   (spe_gbb,     0x1b2)
-EMIT_R   (spe_gbh,     0x1b1)
-EMIT_R   (spe_gb,      0x1b0)
-EMIT_RR  (spe_avgb,    0x0d3)
-EMIT_RR  (spe_absdb,   0x053)
-EMIT_RR  (spe_sumb,    0x253)
-EMIT_R   (spe_xsbh,    0x2b6)
-EMIT_R   (spe_xshw,    0x2ae)
-EMIT_R   (spe_xswd,    0x2a6)
-EMIT_RR  (spe_and,     0x0c1)
-EMIT_RR  (spe_andc,    0x2c1)
-EMIT_RI10s(spe_andbi,   0x016)
-EMIT_RI10s(spe_andhi,   0x015)
-EMIT_RI10s(spe_andi,    0x014)
-EMIT_RR  (spe_or,      0x041)
-EMIT_RR  (spe_orc,     0x2c9)
-EMIT_RI10s(spe_orbi,    0x006)
-EMIT_RI10s(spe_orhi,    0x005)
-EMIT_RI10s(spe_ori,     0x004)
-EMIT_R   (spe_orx,     0x1f0)
-EMIT_RR  (spe_xor,     0x241)
-EMIT_RI10s(spe_xorbi,   0x046)
-EMIT_RI10s(spe_xorhi,   0x045)
-EMIT_RI10s(spe_xori,    0x044)
-EMIT_RR  (spe_nand,    0x0c9)
-EMIT_RR  (spe_nor,     0x049)
-EMIT_RR  (spe_eqv,     0x249)
-EMIT_RRR (spe_selb,    0x008)
-EMIT_RRR (spe_shufb,   0x00b)
-
-
-/* Shift and rotate instructions
- */
-EMIT_RR  (spe_shlh,      0x05f)
-EMIT_RI7 (spe_shlhi,     0x07f)
-EMIT_RR  (spe_shl,       0x05b)
-EMIT_RI7 (spe_shli,      0x07b)
-EMIT_RR  (spe_shlqbi,    0x1db)
-EMIT_RI7 (spe_shlqbii,   0x1fb)
-EMIT_RR  (spe_shlqby,    0x1df)
-EMIT_RI7 (spe_shlqbyi,   0x1ff)
-EMIT_RR  (spe_shlqbybi,  0x1cf)
-EMIT_RR  (spe_roth,      0x05c)
-EMIT_RI7 (spe_rothi,     0x07c)
-EMIT_RR  (spe_rot,       0x058)
-EMIT_RI7 (spe_roti,      0x078)
-EMIT_RR  (spe_rotqby,    0x1dc)
-EMIT_RI7 (spe_rotqbyi,   0x1fc)
-EMIT_RR  (spe_rotqbybi,  0x1cc)
-EMIT_RR  (spe_rotqbi,    0x1d8)
-EMIT_RI7 (spe_rotqbii,   0x1f8)
-EMIT_RR  (spe_rothm,     0x05d)
-EMIT_RI7 (spe_rothmi,    0x07d)
-EMIT_RR  (spe_rotm,      0x059)
-EMIT_RI7 (spe_rotmi,     0x079)
-EMIT_RR  (spe_rotqmby,   0x1dd)
-EMIT_RI7 (spe_rotqmbyi,  0x1fd)
-EMIT_RR  (spe_rotqmbybi, 0x1cd)
-EMIT_RR  (spe_rotqmbi,   0x1c9)
-EMIT_RI7 (spe_rotqmbii,  0x1f9)
-EMIT_RR  (spe_rotmah,    0x05e)
-EMIT_RI7 (spe_rotmahi,   0x07e)
-EMIT_RR  (spe_rotma,     0x05a)
-EMIT_RI7 (spe_rotmai,    0x07a)
-
-
-/* Compare, branch, and halt instructions
- */
-EMIT_RR  (spe_heq,       0x3d8)
-EMIT_RI10(spe_heqi,      0x07f)
-EMIT_RR  (spe_hgt,       0x258)
-EMIT_RI10(spe_hgti,      0x04f)
-EMIT_RR  (spe_hlgt,      0x2d8)
-EMIT_RI10(spe_hlgti,     0x05f)
-EMIT_RR  (spe_ceqb,      0x3d0)
-EMIT_RI10(spe_ceqbi,     0x07e)
-EMIT_RR  (spe_ceqh,      0x3c8)
-EMIT_RI10(spe_ceqhi,     0x07d)
-EMIT_RR  (spe_ceq,       0x3c0)
-EMIT_RI10(spe_ceqi,      0x07c)
-EMIT_RR  (spe_cgtb,      0x250)
-EMIT_RI10(spe_cgtbi,     0x04e)
-EMIT_RR  (spe_cgth,      0x248)
-EMIT_RI10(spe_cgthi,     0x04d)
-EMIT_RR  (spe_cgt,       0x240)
-EMIT_RI10(spe_cgti,      0x04c)
-EMIT_RR  (spe_clgtb,     0x2d0)
-EMIT_RI10(spe_clgtbi,    0x05e)
-EMIT_RR  (spe_clgth,     0x2c8)
-EMIT_RI10(spe_clgthi,    0x05d)
-EMIT_RR  (spe_clgt,      0x2c0)
-EMIT_RI10(spe_clgti,     0x05c)
-EMIT_I16 (spe_br,        0x064)
-EMIT_I16 (spe_bra,       0x060)
-EMIT_RI16(spe_brsl,      0x066)
-EMIT_RI16(spe_brasl,     0x062)
-EMIT_RI16(spe_brnz,      0x042)
-EMIT_RI16(spe_brz,       0x040)
-EMIT_RI16(spe_brhnz,     0x046)
-EMIT_RI16(spe_brhz,      0x044)
-
-/* Control instructions
- */
-EMIT     (spe_lnop,      0x001)
-
-extern void
-spe_lqd(struct spe_function *p, int rT, int rA, int offset);
-
-extern void
-spe_stqd(struct spe_function *p, int rT, int rA, int offset);
-
-extern void spe_bi(struct spe_function *p, int rA, int d, int e);
-extern void spe_iret(struct spe_function *p, int rA, int d, int e);
-extern void spe_bisled(struct spe_function *p, int rT, int rA,
-    int d, int e);
-extern void spe_bisl(struct spe_function *p, int rT, int rA,
-    int d, int e);
-extern void spe_biz(struct spe_function *p, int rT, int rA,
-    int d, int e);
-extern void spe_binz(struct spe_function *p, int rT, int rA,
-    int d, int e);
-extern void spe_bihz(struct spe_function *p, int rT, int rA,
-    int d, int e);
-extern void spe_bihnz(struct spe_function *p, int rT, int rA,
-    int d, int e);
-
-
-/** Load/splat immediate float into rT. */
-extern void
-spe_load_float(struct spe_function *p, int rT, float x);
-
-/** Load/splat immediate int into rT. */
-extern void
-spe_load_int(struct spe_function *p, int rT, int i);
-
-/** Load/splat immediate unsigned int into rT. */
-extern void
-spe_load_uint(struct spe_function *p, int rT, uint ui);
-
-/** And immediate value into rT. */
-extern void
-spe_and_uint(struct spe_function *p, int rT, int rA, uint ui);
-
-/** Xor immediate value into rT. */
-extern void
-spe_xor_uint(struct spe_function *p, int rT, int rA, uint ui);
-
-/** Compare equal with immediate value. */
-extern void
-spe_compare_equal_uint(struct spe_function *p, int rT, int rA, uint ui);
-
-/** Compare greater with immediate value. */
-extern void
-spe_compare_greater_uint(struct spe_function *p, int rT, int rA, uint ui);
-
-/** Replicate word 0 of rA across rT. */
-extern void
-spe_splat(struct spe_function *p, int rT, int rA);
-
-/** rT = complement_all_bits(rA). */
-extern void
-spe_complement(struct spe_function *p, int rT, int rA);
-
-/** rT = rA. */
-extern void
-spe_move(struct spe_function *p, int rT, int rA);
-
-/** rT = {0,0,0,0}. */
-extern void
-spe_zero(struct spe_function *p, int rT);
-
-/** rT = splat(rA, word) */
-extern void
-spe_splat_word(struct spe_function *p, int rT, int rA, int word);
-
-/** rT = float min(rA, rB) */
-extern void
-spe_float_min(struct spe_function *p, int rT, int rA, int rB);
-
-/** rT = float max(rA, rB) */
-extern void
-spe_float_max(struct spe_function *p, int rT, int rA, int rB);
-
-
-/* Floating-point instructions
- */
-EMIT_RR  (spe_fa,         0x2c4)
-EMIT_RR  (spe_dfa,        0x2cc)
-EMIT_RR  (spe_fs,         0x2c5)
-EMIT_RR  (spe_dfs,        0x2cd)
-EMIT_RR  (spe_fm,         0x2c6)
-EMIT_RR  (spe_dfm,        0x2ce)
-EMIT_RRR (spe_fma,        0x00e)
-EMIT_RR  (spe_dfma,       0x35c)
-EMIT_RRR (spe_fnms,       0x00d)
-EMIT_RR  (spe_dfnms,      0x35e)
-EMIT_RRR (spe_fms,        0x00f)
-EMIT_RR  (spe_dfms,       0x35d)
-EMIT_RR  (spe_dfnma,      0x35f)
-EMIT_R   (spe_frest,      0x1b8)
-EMIT_R   (spe_frsqest,    0x1b9)
-EMIT_RR  (spe_fi,         0x3d4)
-EMIT_RI8 (spe_csflt,      0x1da, 155)
-EMIT_RI8 (spe_cflts,      0x1d8, 173)
-EMIT_RI8 (spe_cuflt,      0x1db, 155)
-EMIT_RI8 (spe_cfltu,      0x1d9, 173)
-EMIT_R   (spe_frds,       0x3b9)
-EMIT_R   (spe_fesd,       0x3b8)
-EMIT_RR  (spe_dfceq,      0x3c3)
-EMIT_RR  (spe_dfcmeq,     0x3cb)
-EMIT_RR  (spe_dfcgt,      0x2c3)
-EMIT_RR  (spe_dfcmgt,     0x2cb)
-EMIT_RI7 (spe_dftsv,      0x3bf)
-EMIT_RR  (spe_fceq,       0x3c2)
-EMIT_RR  (spe_fcmeq,      0x3ca)
-EMIT_RR  (spe_fcgt,       0x2c2)
-EMIT_RR  (spe_fcmgt,      0x2ca)
-EMIT_R   (spe_fscrwr,     0x3ba)
-EMIT_    (spe_fscrrd,     0x398)
-
-
-/* Channel instructions
- */
-EMIT_R   (spe_rdch,       0x00d)
-EMIT_R   (spe_rdchcnt,    0x00f)
-EMIT_R   (spe_wrch,       0x10d)
-
-
-#ifdef UNDEF_EMIT_MACROS
-#undef EMIT
-#undef EMIT_
-#undef EMIT_R
-#undef EMIT_RR
-#undef EMIT_RRR
-#undef EMIT_RI7
-#undef EMIT_RI8
-#undef EMIT_RI10
-#undef EMIT_RI10s
-#undef EMIT_RI16
-#undef EMIT_RI18
-#undef EMIT_I16
-#undef UNDEF_EMIT_MACROS
-#endif /* EMIT_ */