summaryrefslogtreecommitdiffstats
path: root/src/gallium/auxiliary/pipebuffer
diff options
context:
space:
mode:
authorJason Ekstrand <[email protected]>2016-01-14 20:42:47 -0800
committerJason Ekstrand <[email protected]>2016-01-15 16:44:02 -0800
commit61b0cfd84ee6fb1273928ee2c8751301ae805eaa (patch)
tree32f4b24e4c720042b5b60a540de528b10e647563 /src/gallium/auxiliary/pipebuffer
parent9870f798beab701a9edda81ff7ccc39f1875d610 (diff)
i965/fs: Always set channel 2 of texture headers in some stages
In the vertex and fragment stages, the hardware is nice to us and leaves g0.2 zerod out for us so we can use it for headers. However, in compute, geometry, and tessellation stages, the hardware is not so nice. In particular, for compute shaders on BDW, the hardware places some debug bits in 23:15. As it happens, bit 15 is interpreted by the sampler as the alpha channel mask. This means that if you use a texturing instruction with a header in a compute shader, you may randomly get the alpha channel disabled. Since channel masks affect the return length of the sampler message, this can lead the GPU to expect a different mlen to the one you specified in the shader and this, in turn, hangs your GPU. Cc: "11.1" <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/gallium/auxiliary/pipebuffer')
0 files changed, 0 insertions, 0 deletions