freedreno/ir3: add some ubo range related asserts

And a comment..  since we are mixing units of bytes/dwords/vec4,
hopefully this will avoid some unit confusion.

Signed-off-by: Rob Clark <[email protected]>

2 files changed, 5 insertions, 1 deletions

diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index f822e9e13e9..da1e148e37a 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -123,7 +123,10 @@ ir3_context_init(struct ir3_compiler *compiler,
 	 *
 	 * Immediates go last mostly because they are inserted in the CP pass
 	 * after the nir -> ir3 frontend.
+	 *
+	 * Note UBO size in bytes should be aligned to vec4
 	 */
+	debug_assert((ctx->so->shader->ubo_state.size % 16) == 0);
 	unsigned constoff = align(ctx->so->shader->ubo_state.size / 16, 4);
 	unsigned ptrsz = ir3_pointer_size(ctx);
 
diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index 46eba2a0c5e..d1d748813af 100644
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -131,7 +131,8 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 	 * the compiler (to worst-case value) since we don't know in
 	 * the assembler what the max addr reg value can be:
 	 */
-	v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
+	v->constlen = MAX2(v->constlen, v->info.max_const + 1);
+	debug_assert(v->constlen < 256);
 
 	fixup_regfootprint(v, gpu_id);