diff options
author | Chia-I Wu <[email protected]> | 2019-02-26 23:29:51 -0800 |
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committer | Chia-I Wu <[email protected]> | 2019-03-11 10:02:13 -0700 |
commit | 9496b377ffe05c0e2abd79fd8158f2ef0d81eb9a (patch) | |
tree | f6f1a6a80d3015e51b655dc428698b9fad9dc6a5 /src/freedreno | |
parent | b4884761e8d85225bcf53d87e6d3bf2572af30c8 (diff) |
turnip: parse VkPipelineRasterizationStateCreateInfo
Diffstat (limited to 'src/freedreno')
-rw-r--r-- | src/freedreno/vulkan/tu_pipeline.c | 111 | ||||
-rw-r--r-- | src/freedreno/vulkan/tu_private.h | 17 |
2 files changed, 128 insertions, 0 deletions
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index bfe60c63bb7..030e107896a 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -47,6 +47,8 @@ struct tu_pipeline_builder const VkGraphicsPipelineCreateInfo *create_info; bool rasterizer_discard; + /* these states are affectd by rasterizer_discard */ + VkSampleCountFlagBits samples; }; static enum tu_dynamic_state_bits @@ -186,6 +188,75 @@ tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor) A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1)); } +static void +tu6_emit_gras_unknowns(struct tu_cs *cs) +{ + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1); + tu_cs_emit(cs, 0x80); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1); + tu_cs_emit(cs, 0x0); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1); + tu_cs_emit(cs, 0x0); +} + +static void +tu6_emit_point_size(struct tu_cs *cs) +{ + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2); + tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) | + A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f)); + tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f)); +} + +static uint32_t +tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info, + VkSampleCountFlagBits samples) +{ + uint32_t gras_su_cntl = 0; + + if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT) + gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT; + if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT) + gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK; + + if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE) + gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW; + + /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */ + + if (rast_info->depthBiasEnable) + gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET; + + if (samples > VK_SAMPLE_COUNT_1_BIT) + gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE; + + return gras_su_cntl; +} + +void +tu6_emit_gras_su_cntl(struct tu_cs *cs, + uint32_t gras_su_cntl, + float line_width) +{ + assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0); + gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f); + + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1); + tu_cs_emit(cs, gras_su_cntl); +} + +void +tu6_emit_depth_bias(struct tu_cs *cs, + float constant_factor, + float clamp, + float slope_factor) +{ + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3); + tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor)); + tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor)); + tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp)); +} + static VkResult tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder *builder, struct tu_pipeline **out_pipeline) @@ -274,6 +345,40 @@ tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder, } static void +tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, + struct tu_pipeline *pipeline) +{ + const VkPipelineRasterizationStateCreateInfo *rast_info = + builder->create_info->pRasterizationState; + + assert(!rast_info->depthClampEnable); + assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL); + + struct tu_cs rast_cs; + tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs); + + /* move to hw ctx init? */ + tu6_emit_gras_unknowns(&rast_cs); + tu6_emit_point_size(&rast_cs); + + const uint32_t gras_su_cntl = + tu6_gras_su_cntl(rast_info, builder->samples); + + if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) + tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth); + + if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) { + tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor, + rast_info->depthBiasClamp, + rast_info->depthBiasSlopeFactor); + } + + pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs); + + pipeline->rast.gras_su_cntl = gras_su_cntl; +} + +static void tu_pipeline_finish(struct tu_pipeline *pipeline, struct tu_device *dev, const VkAllocationCallbacks *alloc) @@ -292,6 +397,7 @@ tu_pipeline_builder_build(struct tu_pipeline_builder *builder, tu_pipeline_builder_parse_dynamic(builder, *pipeline); tu_pipeline_builder_parse_input_assembly(builder, *pipeline); tu_pipeline_builder_parse_viewport(builder, *pipeline); + tu_pipeline_builder_parse_rasterization(builder, *pipeline); /* we should have reserved enough space upfront such that the CS never * grows @@ -318,6 +424,11 @@ tu_pipeline_builder_init_graphics( builder->rasterizer_discard = create_info->pRasterizationState->rasterizerDiscardEnable; + + if (builder->rasterizer_discard) + builder->samples = VK_SAMPLE_COUNT_1_BIT; + else + builder->samples = create_info->pMultisampleState->rasterizationSamples; } VkResult diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h index 2828228184a..31f5364774e 100644 --- a/src/freedreno/vulkan/tu_private.h +++ b/src/freedreno/vulkan/tu_private.h @@ -996,6 +996,12 @@ struct tu_pipeline { struct tu_cs_entry state_ib; } vp; + + struct + { + uint32_t gras_su_cntl; + struct tu_cs_entry state_ib; + } rast; }; void @@ -1004,6 +1010,17 @@ tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport); void tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor); +void +tu6_emit_gras_su_cntl(struct tu_cs *cs, + uint32_t gras_su_cntl, + float line_width); + +void +tu6_emit_depth_bias(struct tu_cs *cs, + float constant_factor, + float clamp, + float slope_factor); + struct tu_userdata_info * tu_lookup_user_sgpr(struct tu_pipeline *pipeline, gl_shader_stage stage, |