diff options
| author | Connor Abbott <[email protected]> | 2020-01-28 13:19:25 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-02-05 13:14:22 +0000 |
| commit | 65197a3ac1cf4303e37927ed3faae47e41ee74e6 (patch) | |
| tree | 4b2b45c1f66126465c014c4e4173edd9da2fd1b4 /src/freedreno | |
| parent | 8be81f8a2a9f3f838cc550aeddf79657608e1008 (diff) | |
freedreno: Fix CP_COND_REG_EXEC bit positions
Reviewed-by: Kristian H. Kristensen <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
Diffstat (limited to 'src/freedreno')
| -rw-r--r-- | src/freedreno/registers/adreno_pm4.xml | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml index 78847fbc021..86c4ff0c5f3 100644 --- a/src/freedreno/registers/adreno_pm4.xml +++ b/src/freedreno/registers/adreno_pm4.xml @@ -1473,11 +1473,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) --> <!-- RM6_BINNING --> - <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/> + <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/> <!-- all others --> - <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/> + <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/> <!-- RM6_BYPASS --> - <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/> + <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/> <bitfield name="MODE" low="28" high="31" type="compare_mode"/> </reg32> |