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authorJonathan Marek <[email protected]>2020-04-22 23:21:20 -0400
committerMarge Bot <[email protected]>2020-04-24 13:11:58 +0000
commitdd49a404106852804544eaf695e46b2f5ccd0a0f (patch)
treea788664408dad17aa2c9429201cc93c1396fbe28 /src/freedreno
parentedc35c1f54a0f72b6c0f01b2156c10c904459b4f (diff)
freedreno/ir3: set even bit for f2f16_rtne
Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4708>
Diffstat (limited to 'src/freedreno')
-rw-r--r--src/freedreno/ir3/ir3_compiler_nir.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 553b772b8ec..c6ed65550a0 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -236,7 +236,6 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
case nir_op_f2f16_rtne:
case nir_op_f2f16_rtz:
case nir_op_f2f16:
- /* TODO how to handle rounding mode? */
case nir_op_i2f16:
case nir_op_u2f16:
dst_type = TYPE_F16;
@@ -276,7 +275,13 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
ir3_context_error(ctx, "invalid conversion op: %u", op);
}
- return ir3_COV(ctx->block, src, src_type, dst_type);
+ struct ir3_instruction *cov =
+ ir3_COV(ctx->block, src, src_type, dst_type);
+
+ if (op == nir_op_f2f16_rtne)
+ cov->regs[0]->flags |= IR3_REG_EVEN;
+
+ return cov;
}
static void