diff options
| author | Jason Ekstrand <[email protected]> | 2018-10-18 11:44:38 -0500 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2018-12-16 21:03:02 +0000 |
| commit | 80e8dfe9dead5a034f8e5ae3f92cc60e99de88b6 (patch) | |
| tree | c2264945096149705cdf621145ce9d4fd4240903 /src/freedreno | |
| parent | b569093566f9138dc8890fe1ef9615d11177d140 (diff) | |
nir: Rename Boolean-related opcodes to include 32 in the name
This is a squash of a bunch of individual changes:
nir/builder: Generate 32-bit bool opcodes transparently
nir/algebraic: Remap Boolean opcodes to the 32-bit variant
Use 32-bit opcodes in the NIR producers and optimizations
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Use 32-bit opcodes in the NIR back-ends
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Tested-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/freedreno')
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index f8155747c52..85f14f354d2 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -458,22 +458,22 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0]->cat5.type = TYPE_F32; break; break; - case nir_op_flt: + case nir_op_flt32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fge: + case nir_op_fge32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_feq: + case nir_op_feq32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fne: + case nir_op_fne32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); @@ -586,38 +586,38 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_ushr: dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0); break; - case nir_op_ilt: + case nir_op_ilt32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ige: + case nir_op_ige32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ieq: + case nir_op_ieq32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ine: + case nir_op_ine32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ult: + case nir_op_ult32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_uge: + case nir_op_uge32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_bcsel: { + case nir_op_b32csel: { struct ir3_instruction *cond = ir3_b2n(b, src[0]); compile_assert(ctx, bs[1] == bs[2]); /* the boolean condition is 32b even if src[1] and src[2] are |