turnip: Support tess for draws

This commit adds tessellation support for draws. We store the IR3
patch type in tu_pipeline so we can use it in tu_emit_draw_*. We then
convert the IR3 patch type to the native adreno patch type and set
the appropriate reg values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

4 files changed, 45 insertions, 7 deletions

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index de4580ae984..9699caefb8d 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2696,6 +2696,7 @@ to upconvert to 32b float internally?
 		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
 		<!-- maybe?  b1 seems always set, so just assume it is for now: -->
 		<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
+		<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
 		<doc>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 1023aedf3af..2f88ca758cb 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -3155,9 +3155,11 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
 
    /* TODO lrz */
 
-   tu_cs_emit_regs(cs,
-                   A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
-                                            pipeline->ia.primitive_restart && draw->indexed));
+   tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(
+         .primitive_restart =
+               pipeline->ia.primitive_restart && draw->indexed,
+         .tess_upper_left_domain_origin =
+               pipeline->tess.upper_left_domain_origin));
 
    if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) {
       cmd->state.shader_const_ib[MESA_SHADER_VERTEX] =
@@ -3310,6 +3312,30 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
    return VK_SUCCESS;
 }
 
+static uint32_t
+compute_tess_draw0(struct tu_pipeline *pipeline)
+{
+   uint32_t patch_type = pipeline->tess.patch_type;
+   uint32_t tess_draw0 = 0;
+   switch (patch_type) {
+   case IR3_TESS_TRIANGLES:
+      tess_draw0 = CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES);
+      break;
+   case IR3_TESS_ISOLINES:
+      tess_draw0 = CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES);
+      break;
+   case IR3_TESS_NONE:
+   case IR3_TESS_QUADS:
+      tess_draw0 = CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS);
+      break;
+   default:
+      unreachable("invalid tess patch type");
+   }
+   if (patch_type != IR3_TESS_NONE)
+      tess_draw0 |= CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
+   return tess_draw0;
+}
+
 static void
 tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
                      struct tu_cs *cs,
@@ -3323,6 +3349,7 @@ tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
 
+   uint32_t tess_draw0 = compute_tess_draw0(cmd->state.pipeline);
    if (draw->indexed) {
       const enum a4xx_index_size index_size =
          tu6_index_size(cmd->state.index_type);
@@ -3337,7 +3364,8 @@ tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
-         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
+         tess_draw0 |
+         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE);
 
       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
       tu_cs_emit(cs, cp_draw_indx);
@@ -3349,7 +3377,8 @@ tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
-         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
+         tess_draw0 |
+         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE);
 
       tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
       tu_cs_emit(cs, cp_draw_indx);
@@ -3373,6 +3402,7 @@ tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
 
+   uint32_t tess_draw0 = compute_tess_draw0(cmd->state.pipeline);
    /* TODO hw binning */
    if (draw->indexed) {
       const enum a4xx_index_size index_size =
@@ -3389,7 +3419,8 @@ tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
-         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
+         tess_draw0 |
+         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE);
 
       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
       tu_cs_emit(cs, cp_draw_indx);
@@ -3403,7 +3434,8 @@ tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
-         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
+         tess_draw0 |
+         COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE);
 
       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
       tu_cs_emit(cs, cp_draw_indx);
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index a0c11b679ab..fe6c346c2d1 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2137,6 +2137,10 @@ tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
    assert(pipeline->ia.primtype == DI_PT_PATCHES0);
    assert(tess_info->patchControlPoints <= 32);
    pipeline->ia.primtype += tess_info->patchControlPoints;
+   const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
+         vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
+   pipeline->tess.upper_left_domain_origin = !domain_info ||
+         domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
    const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
    const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
    pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h
index c12aab2a196..df843ee2789 100644
--- a/src/freedreno/vulkan/tu_private.h
+++ b/src/freedreno/vulkan/tu_private.h
@@ -1110,6 +1110,7 @@ struct tu_pipeline
       uint32_t per_patch_output_size;
       uint32_t hs_bo_regid;
       uint32_t ds_bo_regid;
+      bool upper_left_domain_origin;
    } tess;
 
    struct