diff options
| author | Connor Abbott <[email protected]> | 2020-05-14 16:34:45 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-14 18:15:31 +0000 |
| commit | 0e0580550e1b4846d3ad7ff738f57063b05089c9 (patch) | |
| tree | e14e7b2298126ead51c7e76c7199fc914ba51737 /src/freedreno | |
| parent | 4aeaef99c003f3c75279d9b400315685ebbba30d (diff) | |
freedreno/a6xx: Document dual-src blending enable bits
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5039>
Diffstat (limited to 'src/freedreno')
| -rw-r--r-- | src/freedreno/registers/a6xx.xml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index a831ccc845d..b3398798ec9 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -2095,6 +2095,7 @@ to upconvert to 32b float internally? </reg32> <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0"> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> </reg32> @@ -2201,6 +2202,7 @@ to upconvert to 32b float internally? <!-- per-mrt enable bit --> <bitfield name="ENABLE_BLEND" low="0" high="7"/> <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> <bitfield name="SAMPLE_MASK" low="16" high="31"/> </reg32> @@ -2964,6 +2966,7 @@ to upconvert to 32b float internally? <reg32 offset="0xa989" name="SP_BLEND_CNTL"> <bitfield name="ENABLED" pos="0" type="boolean"/> <bitfield name="UNK8" pos="8" type="boolean"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> </reg32> <reg32 offset="0xa98a" name="SP_SRGB_CNTL"> @@ -2988,6 +2991,7 @@ to upconvert to 32b float internally? <bitfield name="RT7" low="28" high="31"/> </reg32> <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0"> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> </reg32> |