freedreno,tu: Don't request fragcoord components not being read.

v1. Replace the existed bool type with new bitfield and edit register
files to take a mask instead of duplicating codes to do masking.

v2. Use fragcoord_compmask != 0 instead of fragcoord_compmask > 0 since
it represents a bitfield.

Tested with
  dEQP-VK.glsl.builtin_var.simple.fragcoord_xyz/w
  dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz/w

Closes: #2680

Signed-off-by: Hyunjun Ko <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4723>

7 files changed, 17 insertions, 41 deletions

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index b3d0556a03e..d40978f574b 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1411,7 +1411,7 @@ get_barycentric_pixel(struct ir3_context *ctx)
 }
 
 static struct ir3_instruction *
-get_frag_coord(struct ir3_context *ctx)
+get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 {
 	if (!ctx->frag_coord) {
 		struct ir3_block *b = ctx->in_block;
@@ -1436,9 +1436,11 @@ get_frag_coord(struct ir3_context *ctx)
 		}
 
 		ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
-		ctx->so->frag_coord = true;
 	}
 
+	ctx->so->fragcoord_compmask |=
+			nir_ssa_def_components_read(&intr->dest.ssa);
+
 	return ctx->frag_coord;
 }
 
@@ -1599,7 +1601,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 		emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
 		break;
 	case nir_intrinsic_load_frag_coord:
-		ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
+		ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
 		break;
 	case nir_intrinsic_load_sample_pos_from_id: {
 		/* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index ecb39481927..e401498612f 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -456,7 +456,8 @@ struct ir3_shader_variant {
 	 *   + From the vert shader, we only need the output regid
 	 */
 
-	bool frag_coord, frag_face, color0_mrt;
+	bool frag_face, color0_mrt;
+	uint8_t fragcoord_compmask;
 
 	/* NOTE: for input/outputs, slot is:
 	 *   gl_vert_attrib  - for VS inputs
diff --git a/src/freedreno/registers/a3xx.xml b/src/freedreno/registers/a3xx.xml
index 93b14e139ff..3605e3ae409 100644
--- a/src/freedreno/registers/a3xx.xml
+++ b/src/freedreno/registers/a3xx.xml
@@ -870,10 +870,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 			controlling blend or readback from GMEM??
 		 -->
 		<bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
-		<bitfield name="XCOORD" pos="14" type="boolean"/>
-		<bitfield name="YCOORD" pos="15" type="boolean"/>
-		<bitfield name="ZCOORD" pos="16" type="boolean"/>
-		<bitfield name="WCOORD" pos="17" type="boolean"/>
+		<bitfield name="COORD_MASK" low="14" high="17" type="hex"/>
 		<bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
 		<bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
 		<bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
diff --git a/src/freedreno/registers/a4xx.xml b/src/freedreno/registers/a4xx.xml
index 0fa914847f3..1c2c48c5e50 100644
--- a/src/freedreno/registers/a4xx.xml
+++ b/src/freedreno/registers/a4xx.xml
@@ -911,11 +911,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SAMPLES" low="13" high="15" type="uint"/>
 	</reg32>
 	<reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
-		<bitfield name="XCOORD" pos="0" type="boolean"/>
-		<bitfield name="YCOORD" pos="1" type="boolean"/>
-		<!-- assuming zcoord/wcoord follows.. -->
-		<bitfield name="ZCOORD" pos="2" type="boolean"/>
-		<bitfield name="WCOORD" pos="3" type="boolean"/>
+		<bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
 		<bitfield name="SAMPLEMASK" pos="4" type="boolean"/>
 		<bitfield name="FACENESS" pos="5" type="boolean"/>
 		<bitfield name="SAMPLEID" pos="6" type="boolean"/>
diff --git a/src/freedreno/registers/a5xx.xml b/src/freedreno/registers/a5xx.xml
index 42726fcebac..945e09e5b36 100644
--- a/src/freedreno/registers/a5xx.xml
+++ b/src/freedreno/registers/a5xx.xml
@@ -1828,10 +1828,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		Also, when that happens, VARYING bits are turned on as well.
 		 -->
 		<bitfield name="UNK3" pos="3" type="boolean"/>
-		<bitfield name="XCOORD" pos="6" type="boolean"/>
-		<bitfield name="YCOORD" pos="7" type="boolean"/>
-		<bitfield name="ZCOORD" pos="8" type="boolean"/>
-		<bitfield name="WCOORD" pos="9" type="boolean"/>
+		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
 	</reg32>
 	<reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
 		<bitfield name="HORZ" low="0" high="9" type="uint"/>
@@ -1982,10 +1979,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
 		Also, when that happens, VARYING bits are turned on as well.
 		 -->
 		<bitfield name="UNK3" pos="3" type="boolean"/>
-		<bitfield name="XCOORD" pos="6" type="boolean"/>
-		<bitfield name="YCOORD" pos="7" type="boolean"/>
-		<bitfield name="ZCOORD" pos="8" type="boolean"/>
-		<bitfield name="WCOORD" pos="9" type="boolean"/>
+		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
 	</reg32>
 	<reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
 		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index fdb091c5b56..a831ccc845d 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1855,10 +1855,7 @@ to upconvert to 32b float internally?
 		<bitfield name="SIZE" pos="3" type="boolean"/>
 		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
 		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
-		<bitfield name="XCOORD" pos="6" type="boolean"/>
-		<bitfield name="YCOORD" pos="7" type="boolean"/>
-		<bitfield name="ZCOORD" pos="8" type="boolean"/>
-		<bitfield name="WCOORD" pos="9" type="boolean"/>
+		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
 	</reg32>
 	<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
 		<bitfield name="HORZ" low="0" high="9" type="uint"/>
@@ -2083,10 +2080,7 @@ to upconvert to 32b float internally?
 		<bitfield name="SIZE" pos="3" type="boolean"/>
 		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
 		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
-		<bitfield name="XCOORD" pos="6" type="boolean"/>
-		<bitfield name="YCOORD" pos="7" type="boolean"/>
-		<bitfield name="ZCOORD" pos="8" type="boolean"/>
-		<bitfield name="WCOORD" pos="9" type="boolean"/>
+		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
 		<bitfield name="UNK10" pos="10" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 33629457289..31ec5ee18a5 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1271,12 +1271,8 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
          CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
-         COND(fs->frag_coord,
-               A6XX_GRAS_CNTL_SIZE |
-               A6XX_GRAS_CNTL_XCOORD |
-               A6XX_GRAS_CNTL_YCOORD |
-               A6XX_GRAS_CNTL_ZCOORD |
-               A6XX_GRAS_CNTL_WCOORD) |
+         COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
+                              A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
          COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
@@ -1287,12 +1283,8 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
-         COND(fs->frag_coord,
-               A6XX_RB_RENDER_CONTROL0_SIZE |
-               A6XX_RB_RENDER_CONTROL0_XCOORD |
-               A6XX_RB_RENDER_CONTROL0_YCOORD |
-               A6XX_RB_RENDER_CONTROL0_ZCOORD |
-               A6XX_RB_RENDER_CONTROL0_WCOORD) |
+         COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
+                              A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
    tu_cs_emit(cs,
          CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |