diff options
| author | Connor Abbott <[email protected]> | 2019-12-16 17:17:38 +0100 |
|---|---|---|
| committer | Connor Abbott <[email protected]> | 2019-12-18 23:08:55 +0100 |
| commit | cfa1fb895ac5a752772f4d0748c1c2bce0c2e653 (patch) | |
| tree | eeb9ea0a9c07521abebd6fe875f9f2416f1562fb /src/freedreno/vulkan | |
| parent | a9a3108be774aea620fa4fc726c33100d9a49add (diff) | |
a6xx: Add more CP packets
And add fields uncovered by looking at the firmware. I think this covers
all the memory, register, and scratch manipulation opcodes that exist on
A6xx, plus one additional nice find for Vulkan and describing a
previously unknown opcode and documenting CP_WAIT_REG_MEM.
Note that the bits for the CP_REG_TO_MEM count, as well as the formula
for computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG,
are changed because the A630 SQE firmware actually does something
different. I haven't investigated older microcodes to see whether this
extends back to A5xx and A4xx, but the only non-A6xx uses of this
field result in the same bit-pattern when using the A6xx bit range and
formula, so it should be safe to change the definition universally.
Reviewed-by: Kristian H. Kristensen <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
Diffstat (limited to 'src/freedreno/vulkan')
| -rw-r--r-- | src/freedreno/vulkan/tu_cmd_buffer.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 49ea11acfaa..caa1a54af14 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -738,7 +738,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd, tu_cs_emit_pkt7(cs, CP_REG_TEST, 1); tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) | A6XX_CP_REG_TEST_0_BIT(0) | - A6XX_CP_REG_TEST_0_UNK25); + A6XX_CP_REG_TEST_0_WAIT_FOR_ME); tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); tu_cs_emit(cs, 0x10000000); @@ -1124,7 +1124,7 @@ tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs) seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true); - tu_cs_emit_pkt7(cs, CP_UNK_A6XX_14, 4); + tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4); tu_cs_emit(cs, 0x00000000); tu_cs_emit_qw(cs, cmd->scratch_bo.iova); tu_cs_emit(cs, seqno); @@ -1217,7 +1217,7 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_pkt7(cs, CP_REG_TEST, 1); tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) | A6XX_CP_REG_TEST_0_BIT(0) | - A6XX_CP_REG_TEST_0_UNK25); + A6XX_CP_REG_TEST_0_WAIT_FOR_ME); tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); tu_cs_emit(cs, 0x10000000); @@ -1231,7 +1231,7 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) */ tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) | - CP_REG_TO_MEM_0_CNT(1 - 1)); + CP_REG_TO_MEM_0_CNT(0)); tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW); tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1); @@ -1401,7 +1401,7 @@ tu6_render_tile(struct tu_cmd_buffer *cmd, tu_cs_emit_pkt7(cs, CP_REG_TEST, 1); tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) | A6XX_CP_REG_TEST_0_BIT(0) | - A6XX_CP_REG_TEST_0_UNK25); + A6XX_CP_REG_TEST_0_WAIT_FOR_ME); tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); tu_cs_emit(cs, 0x10000000); |