turnip: fix RENDER_COMPONENTS value

This fixes render_components being 0 when mrt_count=8, because shift by 32
is UB and in arm64 it ends up shifting by 0. This fixes tests with 8 MRTs.

Fixes the 3d path sysmem CmdClearAttachments to set RENDER_COMPONENTS, as
it was previously relying on tu6_emit_mrt setting it, but it is now part of
the pipeline state.

Also switch back to the previous behavior of not setting render components
for VK_ATTACHMENT_UNUSED attachments: we don't update the MRT state for
such attachments so we definitely don't want to be trying writing to those.

Fixes: 078aa9df8daff60e52a66d8f ("tu: Move RENDER_COMPONENTS setting to pipeline state")

Signed-off-by: Jonathan Marek <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5292>

1 files changed, 9 insertions, 4 deletions

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 54c5103aa3f..5b93306a30e 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -302,6 +302,7 @@ struct tu_pipeline_builder
    uint32_t color_attachment_count;
    VkFormat color_attachment_formats[MAX_RTS];
    VkFormat depth_attachment_format;
+   uint32_t render_components;
 };
 
 static enum tu_dynamic_state_bits
@@ -1337,7 +1338,8 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
 static void
 tu6_emit_fs_outputs(struct tu_cs *cs,
                     const struct ir3_shader_variant *fs,
-                    uint32_t mrt_count, bool dual_src_blend)
+                    uint32_t mrt_count, bool dual_src_blend,
+                    uint32_t render_components)
 {
    uint32_t smask_regid, posz_regid;
 
@@ -1354,8 +1356,6 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
          fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
    }
 
-   uint32_t render_components = (1 << (4 * mrt_count)) - 1;
-
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
                   A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
@@ -1596,7 +1596,8 @@ tu6_emit_program(struct tu_cs *cs,
    tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
    tu6_emit_fs_inputs(cs, fs);
    tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
-                       builder->use_dual_src_blend);
+                       builder->use_dual_src_blend,
+                       builder->render_components);
 
    tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
       binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
@@ -2632,11 +2633,15 @@ tu_pipeline_builder_init_graphics(
 
          builder->color_attachment_formats[i] = pass->attachments[a].format;
          builder->use_color_attachments = true;
+         builder->render_components |= 0xf << (i * 4);
       }
 
       if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
          builder->color_attachment_count++;
          builder->use_dual_src_blend = true;
+         /* dual source blending has an extra fs output in the 2nd slot */
+         if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
+            builder->render_components |= 0xf << 4;
       }
    }
 }