diff options
| author | Hyunjun Ko <[email protected]> | 2020-04-06 05:16:21 +0000 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-23 01:14:19 +0000 |
| commit | 0edff5123c4f27ff0f8e35d29c2c45a230d3f939 (patch) | |
| tree | c7dcce9b4005aa455dcf5d0701964d2db6179ad8 /src/freedreno/vulkan/tu_pipeline.c | |
| parent | e892733b80fb2ecf4f48787116e47b8230fcf951 (diff) | |
turnip: Skip unused regs when setting up streamout buffers
Fixes: 374406a7c420d266f920461f904864a94dc1b8c8
Signed-off-by: Hyunjun Ko <[email protected]>
Reviewed-by: Brian Ho <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4604>
Diffstat (limited to 'src/freedreno/vulkan/tu_pipeline.c')
| -rw-r--r-- | src/freedreno/vulkan/tu_pipeline.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index d9ffa2411fe..b2d5b69393c 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -827,6 +827,10 @@ tu6_setup_streamout(const struct ir3_shader_variant *v, unsigned k = out->register_index; unsigned idx; + /* Skip it, if there's an unused reg in the middle of outputs. */ + if (v->outputs[k].regid == INVALID_REG) + continue; + tf->ncomp[out->output_buffer] += out->num_components; /* linkage map sorted by order frag shader wants things, so |