diff options
| author | Eric Anholt <[email protected]> | 2020-01-21 12:24:49 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-23 17:38:29 +0000 |
| commit | b327501dbf946279c8dff55566af73821d0d576e (patch) | |
| tree | 9fd7eeb21c36ef31f3db1d6b9c5440af36704bda /src/freedreno/ir3 | |
| parent | 876824908db342f83cebb7845d01b713f85b577a (diff) | |
turnip: Add support for fine derivatives.
This does appear to be the required instruction sequence (dsxpp_1 dst src;
dsxpp_1.p dst src) as dropping either instruction fails the testsuite.
Fixes dEQP-VK.glsl.derivate.*
Reviewed-by: Jonathan Marek <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3494>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3494>
Diffstat (limited to 'src/freedreno/ir3')
| -rw-r--r-- | src/freedreno/ir3/ir3.h | 2 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 8 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_legalize.c | 7 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_shader.h | 2 |
4 files changed, 19 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index b5135fa4017..461ff633205 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1437,7 +1437,9 @@ INSTR1(SQRT) /* cat5 instructions: */ INSTR1(DSX) +INSTR1(DSXPP_1) INSTR1(DSY) +INSTR1(DSYPP_1) INSTR1F(3D, DSX) INSTR1F(3D, DSY) INSTR1(RGETPOS) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 602b3612165..51715025561 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -467,12 +467,20 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0] = ir3_DSX(b, src[0], 0); dst[0]->cat5.type = TYPE_F32; break; + case nir_op_fddx_fine: + dst[0] = ir3_DSXPP_1(b, src[0], 0); + dst[0]->cat5.type = TYPE_F32; + break; case nir_op_fddy: case nir_op_fddy_coarse: dst[0] = ir3_DSY(b, src[0], 0); dst[0]->cat5.type = TYPE_F32; break; break; + case nir_op_fddy_fine: + dst[0] = ir3_DSYPP_1(b, src[0], 0); + dst[0]->cat5.type = TYPE_F32; + break; case nir_op_flt16: case nir_op_flt32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index 7894b75c0e8..db21507181c 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -246,6 +246,13 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) list_addtail(&n->node, &block->instr_list); } + if (n->opc == OPC_DSXPP_1 || n->opc == OPC_DSYPP_1) { + struct ir3_instruction *op_p = ir3_instr_clone(n); + op_p->flags = IR3_INSTR_P; + + ctx->so->need_fine_derivatives = true; + } + if (is_sfu(n)) regmask_set(&state->needs_ss, n->regs[0]); diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index f056a3e5cd6..e6765985676 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -564,6 +564,8 @@ struct ir3_shader_variant { /* do we need derivatives: */ bool need_pixlod; + bool need_fine_derivatives; + /* do we have kill, image write, etc (which prevents early-z): */ bool no_earlyz; |