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authorRob Clark <[email protected]>2019-04-30 10:05:30 -0700
committerRob Clark <[email protected]>2019-05-02 11:19:22 -0700
commit650246523b622341ce47909ba0e45d2b170dec15 (patch)
tree7bacd5a39ea8386601b1535f05711970b41747a4 /src/freedreno/ir3
parent0704ddb2e5845ed296586a19c3eccd83cac74182 (diff)
freedreno/ir3: fb read support
Lower load_output to txf_ms_fb and add support for the new texture fetch instruction. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
Diffstat (limited to 'src/freedreno/ir3')
-rw-r--r--src/freedreno/ir3/ir3_compiler_nir.c28
-rw-r--r--src/freedreno/ir3/ir3_nir.c6
-rw-r--r--src/freedreno/ir3/ir3_shader.h6
3 files changed, 33 insertions, 7 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 3c813c73ae0..f1d9b53c7c4 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1756,12 +1756,9 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
case 3: opc = OPC_GATHER4A; break;
}
break;
+ case nir_texop_txf_ms_fb:
case nir_texop_txf_ms: opc = OPC_ISAMM; break;
- case nir_texop_txs:
- case nir_texop_query_levels:
- case nir_texop_texture_samples:
- case nir_texop_samples_identical:
- case nir_texop_txf_ms_mcs:
+ default:
ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
return;
}
@@ -1838,7 +1835,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
/* NOTE a3xx (and possibly a4xx?) might be different, using isaml
* with scaled x coord according to requested sample:
*/
- if (tex->op == nir_texop_txf_ms) {
+ if (opc == OPC_ISAMM) {
if (ctx->compiler->txf_ms_with_isaml) {
/* the samples are laid out in x dimension as
* 0 1 2 3
@@ -1897,7 +1894,24 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
if (opc == OPC_GETLOD)
type = TYPE_U32;
- struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
+ struct ir3_instruction *samp_tex;
+
+ if (tex->op == nir_texop_txf_ms_fb) {
+ /* only expect a single txf_ms_fb per shader: */
+ compile_assert(ctx, !ctx->so->fb_read);
+ compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
+
+ ctx->so->fb_read = true;
+ samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
+ create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
+ }, 2);
+
+ ctx->so->num_samp++;
+ } else {
+ samp_tex = get_tex_samp_tex_src(ctx, tex);
+ }
+
struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 43b9c4d7287..dffcf5f5ab7 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -216,6 +216,12 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
* and not again on any potential 2nd variant lowering pass:
*/
OPT_V(s, ir3_nir_apply_trig_workarounds);
+
+ /* This wouldn't hurt to run multiple times, but there is
+ * no need to:
+ */
+ if (shader->type == MESA_SHADER_FRAGMENT)
+ OPT_V(s, nir_lower_fb_read);
}
OPT_V(s, nir_lower_tex, &tex_options);
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 4e8ab085d7e..7c1dc38de23 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -434,6 +434,12 @@ struct ir3_shader_variant {
/* number of samplers/textures (which are currently 1:1): */
int num_samp;
+ /* is there an implicit sampler to read framebuffer (FS only).. if
+ * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
+ * the last "real" texture)
+ */
+ bool fb_read;
+
/* do we have one or more SSBO instructions: */
bool has_ssbo;