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authorEric Anholt <[email protected]>2020-04-21 16:02:29 -0700
committerMarge Bot <[email protected]>2020-04-21 23:30:53 +0000
commit2f4a3c1ca07e63b725c6eb4f013c5ee9efb0c1a0 (patch)
tree3e01353d47f9bf861ed41b738d522971588150ac /src/freedreno/ir3
parenteab73799d16ea142dcbcabb6d5bedf860b5c9af7 (diff)
freedreno/ir3: Drop handling FRAG_RESULT_DEPTH writing to .z
Since we consume NIR, we get FRAG_RESULT_DEPTH in .x. Something must have been working out for this code to not be trying to get an undefined value, but go ahead and drop it now. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4668>
Diffstat (limited to 'src/freedreno/ir3')
-rw-r--r--src/freedreno/ir3/ir3_compiler_nir.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index d9152416e4d..a82faee998e 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3150,12 +3150,10 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
unsigned n = out->data.driver_location;
unsigned frac = out->data.location_frac;
unsigned slot = out->data.location;
- unsigned comp = 0;
if (ctx->so->type == MESA_SHADER_FRAGMENT) {
switch (slot) {
case FRAG_RESULT_DEPTH:
- comp = 2; /* tgsi will write to .z component */
so->writes_pos = true;
break;
case FRAG_RESULT_COLOR:
@@ -3213,7 +3211,7 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
so->outputs[n].slot = slot;
- so->outputs[n].regid = regid(n, comp);
+ so->outputs[n].regid = regid(n, 0);
so->outputs_count = MAX2(so->outputs_count, n + 1);
for (int i = 0; i < ncomp; i++) {