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authorRob Clark <[email protected]>2019-05-02 09:37:21 -0700
committerRob Clark <[email protected]>2019-05-02 11:19:22 -0700
commitca3eb5db665cbcc2de5a5d3158e3dc68f86e5822 (patch)
treeefef1d5fd96eb368b3f1aa7ede612ffa3a45aeec /src/freedreno/ir3/ir3_shader.c
parente941faf3e83fa0d5ce0bd6e67119e8d6bf975502 (diff)
freedreno/ir3: add some ubo range related asserts
And a comment.. since we are mixing units of bytes/dwords/vec4, hopefully this will avoid some unit confusion. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/freedreno/ir3/ir3_shader.c')
-rw-r--r--src/freedreno/ir3/ir3_shader.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index 46eba2a0c5e..d1d748813af 100644
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -131,7 +131,8 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
* the compiler (to worst-case value) since we don't know in
* the assembler what the max addr reg value can be:
*/
- v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
+ v->constlen = MAX2(v->constlen, v->info.max_const + 1);
+ debug_assert(v->constlen < 256);
fixup_regfootprint(v, gpu_id);