diff options
| author | Connor Abbott <[email protected]> | 2020-04-15 14:18:03 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-15 22:38:20 +0000 |
| commit | abcfb6437062f469335d27d5ef60ecf20272dc26 (patch) | |
| tree | b6c5ba91f6668837dc3d9447a5b952939dc647b3 /src/freedreno/ir3/ir3_compiler_nir.c | |
| parent | 2d489f76f48095799392a915dcedc074bbb5e52a (diff) | |
ir3: Fix LDC offset units
I had missed that LDC actually uses vec4 units for its offset. This
means that we have to create a new instruction, and lower it in
ir3_nir_lower_io_offsets, similar to the existing SSBO instructions.
Unfortunately we can't assume that loads are always vec4-aligned, so we
have to use the alignment information that NIR gives us. Unfortunately,
it's currently woefully inadequate, and will have to be fixed to give us
good codegen in the future.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4568>
Diffstat (limited to 'src/freedreno/ir3/ir3_compiler_nir.c')
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 8c676b2f3ce..d9152416e4d 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -748,8 +748,8 @@ emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0]; struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0); ldc->regs[0]->wrmask = MASK(ncomp); - ldc->cat6.iim_val = intr->num_components; - ldc->cat6.d = 1; + ldc->cat6.iim_val = ncomp; + ldc->cat6.d = nir_intrinsic_base(intr); ldc->cat6.type = TYPE_U32; nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]); @@ -768,13 +768,6 @@ static void emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction **dst) { - if (ir3_bindless_resource(intr->src[0])) { - /* TODO: We should be using ldc for non-bindless things on a6xx as - * well. - */ - emit_intrinsic_load_ubo_ldc(ctx, intr, dst); - return; - } struct ir3_block *b = ctx->block; struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1; /* UBO addresses are the first driver params, but subtract 2 here to @@ -1612,6 +1605,9 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_load_ubo: emit_intrinsic_load_ubo(ctx, intr, dst); break; + case nir_intrinsic_load_ubo_ir3: + emit_intrinsic_load_ubo_ldc(ctx, intr, dst); + break; case nir_intrinsic_load_frag_coord: ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4); break; |