diff options
| author | Rob Clark <[email protected]> | 2019-05-31 07:40:16 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-05-31 12:58:33 -0700 |
| commit | 8b7bf5e07aafe8c3ff17fbd49e6f516b2ddab458 (patch) | |
| tree | 83dc4f95bcb60972d5f6fb22b13ab9db7deb9b10 /src/freedreno/ir3/ir3_compiler_nir.c | |
| parent | 8eaa2d502131bdce874603f522eabc4a5719f2e6 (diff) | |
freedreno/ir3: fix constlen versus indirect UBO
If we access the address of the UBO indirectly, and there is no higher
const emitted w/ direct access (like an immediate lowered to uniform)
the assembler won't figure out the correct constlen.
Fixes:
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_vertex
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_vertex
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_fragment
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/freedreno/ir3/ir3_compiler_nir.c')
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index be141ce4e4a..f4192b961d7 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -699,6 +699,13 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, } else { base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz)); base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz)); + + /* NOTE: since relative addressing is used, make sure constlen is + * at least big enough to cover all the UBO addresses, since the + * assembler won't know what the max address reg is. + */ + ctx->so->constlen = MAX2(ctx->so->constlen, + const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz)); } /* note: on 32bit gpu's base_hi is ignored and DCE'd */ @@ -1256,7 +1263,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) * since we don't know in the assembler what the max * addr reg value can be: */ - ctx->so->constlen = ctx->s->num_uniforms; + ctx->so->constlen = MAX2(ctx->so->constlen, ctx->s->num_uniforms); } break; case nir_intrinsic_load_ubo: |