freedreno/ir3: add Sethi–Ullman numbering pass

Signed-off-by: Rob Clark <[email protected]>

1 files changed, 18 insertions, 3 deletions

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 53e56edb3c4..e38ef9fcb66 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -29,8 +29,9 @@
 
 #include "compiler/shader_enums.h"
 
-#include "util/u_debug.h"
+#include "util/bitscan.h"
 #include "util/list.h"
+#include "util/u_debug.h"
 
 #include "instr-a3xx.h"
 
@@ -292,6 +293,9 @@ struct ir3_instruction {
 	 */
 	void *data;
 
+	int sun;            /* Sethi–Ullman number, used by sched */
+	int use_count;      /* currently just updated/used by cp */
+
 	/* Used during CP and RA stages.  For fanin and shader inputs/
 	 * outputs where we need a sequence of consecutive registers,
 	 * keep track of each src instructions left (ie 'n-1') and right
@@ -363,8 +367,6 @@ struct ir3_instruction {
 	/* Entry in ir3_block's instruction list: */
 	struct list_head node;
 
-	int use_count;      /* currently just updated/used by cp */
-
 #ifdef DEBUG
 	uint32_t serialno;
 #endif
@@ -443,6 +445,8 @@ struct ir3 {
 	/* List of ir3_array's: */
 	struct list_head array_list;
 
+	unsigned max_sun;   /* max Sethi–Ullman number */
+
 #ifdef DEBUG
 	unsigned block_count, instr_count;
 #endif
@@ -739,6 +743,14 @@ static inline bool is_meta(struct ir3_instruction *instr)
 	return (opc_cat(instr->opc) == -1);
 }
 
+static inline unsigned dest_regs(struct ir3_instruction *instr)
+{
+	if ((instr->regs_count == 0) || is_store(instr))
+		return 0;
+
+	return util_last_bit(instr->regs[0]->wrmask);
+}
+
 static inline bool writes_addr(struct ir3_instruction *instr)
 {
 	if (instr->regs_count > 0) {
@@ -999,6 +1011,9 @@ void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
 /* group neighbors and insert mov's to resolve conflicts: */
 void ir3_group(struct ir3 *ir);
 
+/* Sethi–Ullman numbering: */
+void ir3_sun(struct ir3 *ir);
+
 /* scheduling: */
 void ir3_sched_add_deps(struct ir3 *ir);
 int ir3_sched(struct ir3 *ir);