freedreno/ir3: sched fixes for addr register usage

A handful of fixes and cleanups:

1) If we split addr/pred, we need the newly created instruction to
   end up in the unscheduled_list
2) Avoid scheduling a write to the address register if there is no
   instruction using the address register that is otherwise ready
   to schedule.  Note that I currently don't bother with the same
   logic for predicate register, since the only instructions using
   predicate (br/kill) don't take any other src registers, so this
   situation should not arise.
3) few other cosmetic cleanups

Signed-off-by: Rob Clark <[email protected]>

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