diff options
| author | Daniel Schürmann <[email protected]> | 2019-02-14 08:19:09 +0100 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-02-25 12:59:43 -0600 |
| commit | 0525bdc2259a541780ca7235a262c406ceb1a6e6 (patch) | |
| tree | e756baaf33b47540d6bde2a0679a8a7a60035412 /src/compiler | |
| parent | c4fb6b0c8110e8f9dc861ab890ad200b7b820acd (diff) | |
nir: Define shifts according to SM5 specification.
SPIR-V shifts are undefined for values >= bitsize, but SM5 shifts
are defined to only use the least significant bits.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/compiler')
| -rw-r--r-- | src/compiler/nir/nir_opcodes.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index d32005846a6..499deb947e8 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -610,10 +610,12 @@ binop("sge", tfloat, "", "(src0 >= src1) ? 1.0f : 0.0f") # Set on Greater or Equ binop("seq", tfloat32, commutative, "(src0 == src1) ? 1.0f : 0.0f") # Set on Equal binop("sne", tfloat32, commutative, "(src0 != src1) ? 1.0f : 0.0f") # Set on Not Equal - -opcode("ishl", 0, tint, [0, 0], [tint, tuint32], "", "src0 << src1") -opcode("ishr", 0, tint, [0, 0], [tint, tuint32], "", "src0 >> src1") -opcode("ushr", 0, tuint, [0, 0], [tuint, tuint32], "", "src0 >> src1") +# SPIRV shifts are undefined for shift-operands >= bitsize, +# but SM5 shifts are defined to use the least significant bits, only +# The NIR definition is according to the SM5 specification. +opcode("ishl", 0, tint, [0, 0], [tint, tuint32], "", "src0 << (src1 & (sizeof(src0) * 8 - 1))") +opcode("ishr", 0, tint, [0, 0], [tint, tuint32], "", "src0 >> (src1 & (sizeof(src0) * 8 - 1))") +opcode("ushr", 0, tuint, [0, 0], [tuint, tuint32], "", "src0 >> (src1 & (sizeof(src0) * 8 - 1))") # bitwise logic operators # |