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authorAlyssa Rosenzweig <[email protected]>2019-11-06 21:47:23 -0500
committerTomeu Vizoso <[email protected]>2019-11-11 15:23:44 +0000
commit03f73c7fc6666c904ec0ad07c6aaaf175bc41291 (patch)
tree236b08b9cf310b93479aa33b1bb4a9cd4a6fc996 /src/compiler/nir
parentee5321f2392f8d98a552750986fa476ab8c13eb3 (diff)
nir: Add load_output_u8_as_fp16_pan intrinsic
This is a single opcode, at least on newer Midgard chips. It's easier to have this represented in NIR rather than trying to optimize out the conversions, so let's add the intrinsic. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
Diffstat (limited to 'src/compiler/nir')
-rw-r--r--src/compiler/nir/nir_intrinsics.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 4658187ea16..ce10dd22d6c 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -836,10 +836,16 @@ intrinsic("load_global_ir3", [2, 1], dest_comp=0, indices=[ACCESS, ALIGN_MUL, AL
# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires
# an sRGB->linear conversion, but linear values should be written to
# raw_output_pan and the hardware handles linear->sRGB.
+#
+# We also have format-specific Midgard intrinsics. There are rather
+# here-be-dragons. load_output_u8_as_fp16_pan does the equivalent of
+# load_raw_out_pan on an RGBA8 UNORM framebuffer followed by u2u16 -> fp16 ->
+# division by 255.
# src[] = { value }
store("raw_output_pan", 1, [])
load("raw_output_pan", 0, [], [CAN_ELIMINATE, CAN_REORDER])
+load("output_u8_as_fp16_pan", 0, [], [CAN_ELIMINATE, CAN_REORDER])
# V3D-specific instrinc for tile buffer color reads.
#