diff options
| author | Caio Marcelo de Oliveira Filho <[email protected]> | 2020-04-28 13:09:27 -0700 |
|---|---|---|
| committer | Caio Marcelo de Oliveira Filho <[email protected]> | 2020-05-01 12:50:37 -0700 |
| commit | 2663759af0edb1ebcee3aa1ff63f846911d16076 (patch) | |
| tree | dcf59ff822066ed4dd969211f989e62c72a761c1 /src/compiler/nir | |
| parent | 4b000b491a49afb12612a3cfeebeca9a528cd5e3 (diff) | |
intel/fs: Add and use a new load_simd_width_intel intrinsic
Intrinsic to get the SIMD width, which not always the same as subgroup
size. Starting with a small scope (Intel), but we can rename it later
to generalize if this turns out useful for other drivers.
Change brw_nir_lower_cs_intrinsics() to use this intrinsic instead of
a width will be passed as argument. The pass also used to optimized
load_subgroup_id for the case that the workgroup fitted into a single
thread (it will be constant zero). This optimization moved together
with lowering of the SIMD.
This is a preparation for letting the drivers call it before the
brw_compile_cs() step.
No shader-db changes in BDW, SKL, ICL and TGL.
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Diffstat (limited to 'src/compiler/nir')
| -rw-r--r-- | src/compiler/nir/nir_intrinsics.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 6ce3ce147b6..611955ffa02 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -645,6 +645,9 @@ system_value("color1", 4) # System value for internal compute shaders in radeonsi. system_value("user_data_amd", 4) +# Number of data items being operated on for a SIMD program. +system_value("simd_width_intel", 1) + # Barycentric coordinate intrinsics. # # These set up the barycentric coordinates for a particular interpolation. |