diff options
| author | Kristian H. Kristensen <[email protected]> | 2019-10-22 19:30:51 -0700 |
|---|---|---|
| committer | Kristian H. Kristensen <[email protected]> | 2019-11-07 16:40:27 -0800 |
| commit | e28fbbd86120955360f814520500ac292c1f32df (patch) | |
| tree | dad0fe27c1b9fdc58a0158f44cfe33ef62f7072c /src/compiler/nir/nir_intrinsics.py | |
| parent | 4915231b8a786466041f34dd3e83f31470d40dde (diff) | |
freedreno/ir3: Implement TCS synchronization intrinsics
We add two new IR3 specific nir intrinsics that map to the new condend
and endpatch instructions.
Signed-off-by: Kristian H. Kristensen <[email protected]>
Acked-by: Eric Anholt <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/compiler/nir/nir_intrinsics.py')
| -rw-r--r-- | src/compiler/nir/nir_intrinsics.py | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 55050a9e058..4658187ea16 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -798,6 +798,14 @@ system_value("tess_factor_base_ir3", 2) system_value("tess_param_base_ir3", 2) system_value("tcs_header_ir3", 1) +# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end +# the shader when src0 is false and is used to narrow down the TCS shader to +# just thread 0 before writing out tessellation levels. +intrinsic("cond_end_ir3", src_comp=[1]) +# end_patch_ir3 is used just before thread 0 exist the TCS and presumably +# signals the TE that the patch is complete and can be tessellated. +intrinsic("end_patch_ir3") + # IR3-specific load/store intrinsics. These access a buffer used to pass data # between geometry stages - perhaps it's explicit access to the vertex cache. |