diff options
| author | Karol Herbst <[email protected]> | 2019-03-18 21:23:59 +0100 |
|---|---|---|
| committer | Karol Herbst <[email protected]> | 2019-03-21 02:58:41 +0000 |
| commit | 71c66c254b8021e2c01b1af9b4d16e18bbd26b48 (patch) | |
| tree | 2b481d11f84adc6c1288295918bd88ff989e3172 /src/compiler/nir/nir_instr_set.c | |
| parent | b95b33a5c777e6c2cb378fb6d4e257b50c3a5a4d (diff) | |
nir: add support for gather offsets
Values inside the offsets parameter of textureGatherOffsets are required to be
constants in the range of [GL_MIN_PROGRAM_TEXTURE_GATHER_OFFSET,
GL_MAX_PROGRAM_TEXTURE_GATHER_OFFSET].
As this range is never outside [-32, 31] for all existing drivers inside mesa,
we can simply store the offsets as a int8_t[4][2] array inside nir_tex_instr.
Right now only Nvidia hardware supports this in hardware, so we can turn this
on inside Nouveau for the NIR path as it is already enabled with the TGSI one.
v2: use memcpy instead of for loops
add missing bits to nir_instr_set
don't show offsets if they are all 0
v3: default offsets aren't all 0
v4: rename offsets -> tg4_offsets
rename nir_tex_instr_has_explicit_offsets -> nir_tex_instr_has_explicit_tg4_offsets
Signed-off-by: Karol Herbst <[email protected]>
Diffstat (limited to 'src/compiler/nir/nir_instr_set.c')
| -rw-r--r-- | src/compiler/nir/nir_instr_set.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_instr_set.c b/src/compiler/nir/nir_instr_set.c index 8f4e971b89a..d106e9ebcae 100644 --- a/src/compiler/nir/nir_instr_set.c +++ b/src/compiler/nir/nir_instr_set.c @@ -200,6 +200,9 @@ hash_tex(uint32_t hash, const nir_tex_instr *instr) hash = HASH(hash, instr->is_new_style_shadow); unsigned component = instr->component; hash = HASH(hash, component); + for (unsigned i = 0; i < 4; ++i) + for (unsigned j = 0; j < 2; ++j) + hash = HASH(hash, instr->tg4_offsets[i][j]); hash = HASH(hash, instr->texture_index); hash = HASH(hash, instr->texture_array_size); hash = HASH(hash, instr->sampler_index); @@ -403,6 +406,10 @@ nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2) return false; } + if (memcmp(tex1->tg4_offsets, tex2->tg4_offsets, + sizeof(tex1->tg4_offsets))) + return false; + return true; } case nir_instr_type_load_const: { |