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| author | Scott D Phillips <[email protected]> | 2018-04-30 10:25:47 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2018-04-30 15:18:36 -0700 |
| commit | 2a08ae3c7cba14b9805d006e1981ba9d762bf241 (patch) | |
| tree | e9f36ce2c3ddd5d852d34197361f11e5abcfa320 /src/compiler/glsl/opt_rebalance_tree.cpp | |
| parent | 682bdaa658d63993e32f95a4244568aeab85642a (diff) | |
i965/tiled_memcpy: ytiled_to_linear a cache line at a time
Similar to the transformation applied to linear_to_ytiled, also align
each readback from the ytiled source to a cacheline (i.e. transfer a
whole cacheline from the source before moving on to the next column).
This will allow us to utilize movntqda (_mm_stream_si128) in a
subsequent patch to obtain near WB readback performance when accessing
the uncached ytiled memory, an order of magnitude improvement.
Reviewed-by: Chris Wilson <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/compiler/glsl/opt_rebalance_tree.cpp')
0 files changed, 0 insertions, 0 deletions