diff options
| author | Eric Anholt <[email protected]> | 2017-11-07 09:51:56 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2017-11-07 12:57:49 -0800 |
| commit | dfff9ce45ef9e2ba61814d7a75b896bbaf970557 (patch) | |
| tree | dea5dbaf7576976bc1903e5a3e3c2dc024a12671 /src/broadcom | |
| parent | 9ccb6621be2f40a74f75efe30d83b7813e3c3f56 (diff) | |
broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.
The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.
Fixes fs-discard-exit-2 on simulation (but not HW).
Diffstat (limited to 'src/broadcom')
| -rw-r--r-- | src/broadcom/compiler/qpu_schedule.c | 8 | ||||
| -rw-r--r-- | src/broadcom/qpu/qpu_instr.c | 30 |
2 files changed, 33 insertions, 5 deletions
diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index dd221e027ec..799da805906 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -201,13 +201,15 @@ process_waddr_deps(struct schedule_state *state, struct schedule_node *n, case V3D_QPU_WADDR_R0: case V3D_QPU_WADDR_R1: case V3D_QPU_WADDR_R2: - case V3D_QPU_WADDR_R3: - case V3D_QPU_WADDR_R4: - case V3D_QPU_WADDR_R5: add_write_dep(state, &state->last_r[waddr - V3D_QPU_WADDR_R0], n); break; + case V3D_QPU_WADDR_R3: + case V3D_QPU_WADDR_R4: + case V3D_QPU_WADDR_R5: + /* Handled by v3d_qpu_writes_r*() checks below. */ + break; case V3D_QPU_WADDR_VPM: case V3D_QPU_WADDR_VPMU: diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c index 7499170de3d..7695e0b9358 100644 --- a/src/broadcom/qpu/qpu_instr.c +++ b/src/broadcom/qpu/qpu_instr.c @@ -602,6 +602,18 @@ v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) bool v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst) { + if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { + if (inst->alu.add.magic_write && + inst->alu.add.waddr == V3D_QPU_WADDR_R3) { + return true; + } + + if (inst->alu.mul.magic_write && + inst->alu.mul.waddr == V3D_QPU_WADDR_R3) { + return true; + } + } + return inst->sig.ldvary || inst->sig.ldvpm; } @@ -613,12 +625,14 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst) if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { if (inst->alu.add.magic_write && - v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) { + (inst->alu.add.waddr == V3D_QPU_WADDR_R4 || + v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) { return true; } if (inst->alu.mul.magic_write && - v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) { + (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 || + v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) { return true; } } @@ -629,6 +643,18 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst) bool v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst) { + if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { + if (inst->alu.add.magic_write && + inst->alu.add.waddr == V3D_QPU_WADDR_R5) { + return true; + } + + if (inst->alu.mul.magic_write && + inst->alu.mul.waddr == V3D_QPU_WADDR_R5) { + return true; + } + } + return inst->sig.ldvary || inst->sig.ldunif; } |