diff options
| author | Eric Anholt <[email protected]> | 2018-04-25 16:16:27 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-04-26 11:30:22 -0700 |
| commit | 089c32eefd2f9afcbfc87349beacbdf9d005cfac (patch) | |
| tree | e67e31331b46fe63dbc46f52ad93c6bfbfab0f08 /src/broadcom | |
| parent | 57ceb95c842215880b7cb416fbdb9545276cfc05 (diff) | |
broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
We don't use TMUWT yet, but we will once we do SSBOs.
Diffstat (limited to 'src/broadcom')
| -rw-r--r-- | src/broadcom/compiler/qpu_validate.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/broadcom/compiler/qpu_validate.c b/src/broadcom/compiler/qpu_validate.c index 492f2e64d09..b459d81b446 100644 --- a/src/broadcom/compiler/qpu_validate.c +++ b/src/broadcom/compiler/qpu_validate.c @@ -247,6 +247,11 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) fail_instr(state, "RF write after THREND"); + + /* GFXH-1625: No TMUWT in the last instruction */ + if (state->last_thrsw_ip - state->ip == 2 && + inst->alu.add.op == V3D_QPU_A_TMUWT) + fail_instr(state, "TMUWT in last instruction"); } if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) { |