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authorEric Anholt <eric@anholt.net>2017-10-24 19:13:17 -0700
committerEric Anholt <eric@anholt.net>2017-10-30 13:31:16 -0700
commit607031f411cfef1c80a4088f16a5bc33d995849c (patch)
treee3601a51bc2e37a53c137d80014b16039bbd416d /src/broadcom
parentd0f7053369920cb4a1d0982b7869ff0577fef961 (diff)
broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.
Improves CLIF dumping output.
Diffstat (limited to 'src/broadcom')
-rw-r--r--src/broadcom/cle/v3d_packet_v33.xml2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 86fc8102145..3be33f41a08 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -528,7 +528,7 @@
</packet>
<packet code="121" name="Tile Rendering Mode Configuration (Z/Stencil config)" cl="R">
- <field name="Address" size="32" start="32" type="address"/>
+ <field name="Address" size="26" start="38" type="address"/>
<field name="Padded height of output image in UIF blocks" size="13" start="25" type="uint"/>