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authorEric Anholt <eric@anholt.net>2018-01-04 10:34:36 -0800
committerEric Anholt <eric@anholt.net>2018-01-12 21:53:38 -0800
commit81ec2ba22975595b4f07c3e8307a8f0a4ec18773 (patch)
treea0872384f5ce5ff12b4dba50f85d6a997614b28b /src/broadcom
parent954a704da3052028da4129cc7757f5f224ee1ffc (diff)
broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.
Diffstat (limited to 'src/broadcom')
-rw-r--r--src/broadcom/qpu/qpu_pack.c34
-rw-r--r--src/broadcom/qpu/tests/qpu_disasm.c6
2 files changed, 40 insertions, 0 deletions
diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index 6630ed4b85f..02aa1b86aa4 100644
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -743,6 +743,19 @@ v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
}
break;
+
+ case V3D_QPU_M_VFMUL:
+ instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
+
+ if (!v3d_qpu_float16_unpack_unpack(((op & 0x7) - 4) & 7,
+ &instr->alu.mul.a_unpack)) {
+ return false;
+ }
+
+ instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
+
+ break;
+
default:
instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
instr->alu.mul.a_unpack = V3D_QPU_UNPACK_NONE;
@@ -1002,6 +1015,27 @@ v3d_qpu_mul_pack(const struct v3d_device_info *devinfo,
break;
}
+ case V3D_QPU_M_VFMUL: {
+ uint32_t packed;
+
+ if (instr->alu.mul.output_pack != V3D_QPU_PACK_NONE)
+ return false;
+
+ if (!v3d_qpu_float16_unpack_pack(instr->alu.mul.a_unpack,
+ &packed)) {
+ return false;
+ }
+ if (instr->alu.mul.a_unpack == V3D_QPU_UNPACK_SWAP_16)
+ opcode = 8;
+ else
+ opcode |= (packed + 4) & 7;
+
+ if (instr->alu.mul.b_unpack != V3D_QPU_UNPACK_NONE)
+ return false;
+
+ break;
+ }
+
default:
break;
}
diff --git a/src/broadcom/qpu/tests/qpu_disasm.c b/src/broadcom/qpu/tests/qpu_disasm.c
index c7f6476def5..59668a86ecc 100644
--- a/src/broadcom/qpu/tests/qpu_disasm.c
+++ b/src/broadcom/qpu/tests/qpu_disasm.c
@@ -40,6 +40,12 @@ static const struct {
{ 33, 0x3c002380b6edb000ull, "or rf0, r3, r3 ; mov vpm, r3" },
{ 33, 0x57403006bbb80000ull, "nop ; fmul r0, rf0, r5 ; ldvpm; ldunif" },
+ /* vfmul input packing */
+ { 33, 0x101e8b6e8aad4000ull, "fmax.nornn rf46, r4.l, r2.l; vfmul.ifnb rf45, r3, r5" },
+ { 33, 0x1857d3c219825000ull, "faddnf.norc r2.l, r5.l, r4; vfmul.ifb rf15, r0.ll, r4; ldunif" },
+ { 33, 0x1c0a0dfde2294000ull, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
+ { 33, 0x2011c89b402cc000ull, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
+
/* branch conditions */
{ 33, 0x02000006002034c0ull, "b.anyap rf19" },
{ 33, 0x02679356b4201000ull, "b.anyap -1268280496" },