diff options
| author | Eric Anholt <[email protected]> | 2018-01-04 15:35:28 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-01-12 21:54:33 -0800 |
| commit | 22a02f3e344d6bc47e3e30949a36d00a9eae84a9 (patch) | |
| tree | 632ed61f4bee7c932baf6383d256c4ec304994cd /src/broadcom/qpu/tests | |
| parent | 55f8a01acae7c4171ccfef301e48dc3cc67f5836 (diff) | |
broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.
Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.
VPM loads also gain the ability to be reordered by packing the row into
the A argument. They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.
Diffstat (limited to 'src/broadcom/qpu/tests')
| -rw-r--r-- | src/broadcom/qpu/tests/qpu_disasm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/broadcom/qpu/tests/qpu_disasm.c b/src/broadcom/qpu/tests/qpu_disasm.c index 27dc184f76e..8d77740edce 100644 --- a/src/broadcom/qpu/tests/qpu_disasm.c +++ b/src/broadcom/qpu/tests/qpu_disasm.c @@ -76,6 +76,10 @@ static const struct { { 41, 0xdb3048eb9d533780ull, "fmax rf43.l, r3.h, rf30; fmul rf35.h, r4, r2.l; ldunifarf.r1" }, { 41, 0x733620471e6ce700ull, "faddnf rf7.l, rf28.h, r1.l; fmul r1, r3.h, r3.abs; ldunifarf.rsqrt2" }, { 41, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3; fmul.pushz rf43.l, r5, r1.h" }, + + /* v4.1 opcodes */ + { 41, 0x3de020c7bdfd200dull, "ldvpmg_in rf7, r2, r2; mov r3, 13" }, + { 41, 0x3de02040f8ff7201ull, "stvpmv 1, rf8 ; mov r1, 1" }, }; static void |