diff options
| author | Eric Anholt <[email protected]> | 2018-07-16 12:35:11 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-07-16 14:39:59 -0700 |
| commit | d661d78464aec0af7d6976512eca155623cbecc2 (patch) | |
| tree | ff609d6aa78d677c160329062edcd1f65ad22494 /src/broadcom/compiler | |
| parent | cec540fbc6f00049b8393b70219b6fe0b303b7b0 (diff) | |
v3d: Apply GFXH-1625 restriction on TMUWT in the end of the shader.
This doesn't affect us yet since we're not doing TMUWTs, but I think we
will for GLES 3.1.
Diffstat (limited to 'src/broadcom/compiler')
| -rw-r--r-- | src/broadcom/compiler/qpu_schedule.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index b404390a799..a2260f8b2a7 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -1073,6 +1073,10 @@ qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c, return false; if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { + /* GFXH-1625: TMUWT not allowed in the final instruction. */ + if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT) + return false; + /* No writing physical registers at the end. */ if (!inst->alu.add.magic_write || !inst->alu.mul.magic_write) { |