diff options
| author | Eric Anholt <[email protected]> | 2018-01-03 21:42:33 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-01-12 21:53:45 -0800 |
| commit | dfee62eed3cacbf77ca3168143be6577849c998d (patch) | |
| tree | aa86205704ae035d857f49201b48829c5408c5f7 /src/broadcom/compiler/vir_to_qpu.c | |
| parent | 81ec2ba22975595b4f07c3e8307a8f0a4ec18773 (diff) | |
broadcom/vc5: Add support for V3Dv4 signal bits.
The WRTMUC replaces the implicit uniform loads in the first two texture
instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.
Diffstat (limited to 'src/broadcom/compiler/vir_to_qpu.c')
| -rw-r--r-- | src/broadcom/compiler/vir_to_qpu.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/broadcom/compiler/vir_to_qpu.c b/src/broadcom/compiler/vir_to_qpu.c index eeb7b0bc291..525638df691 100644 --- a/src/broadcom/compiler/vir_to_qpu.c +++ b/src/broadcom/compiler/vir_to_qpu.c @@ -264,7 +264,14 @@ v3d_generate_code_block(struct v3d_compile *c, } if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) { - if (qinst->qpu.alu.add.op != V3D_QPU_A_NOP) { + if (v3d_qpu_sig_writes_address(c->devinfo, + &qinst->qpu.sig)) { + assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP); + assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); + + qinst->qpu.sig_addr = dst.index; + qinst->qpu.sig_magic = dst.magic; + } else if (qinst->qpu.alu.add.op != V3D_QPU_A_NOP) { assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); if (nsrc >= 1) { set_src(&qinst->qpu, |