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authorEric Anholt <[email protected]>2018-01-03 21:42:33 -0800
committerEric Anholt <[email protected]>2018-01-12 21:53:45 -0800
commitdfee62eed3cacbf77ca3168143be6577849c998d (patch)
treeaa86205704ae035d857f49201b48829c5408c5f7 /src/broadcom/compiler/vir_register_allocate.c
parent81ec2ba22975595b4f07c3e8307a8f0a4ec18773 (diff)
broadcom/vc5: Add support for V3Dv4 signal bits.
The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
Diffstat (limited to 'src/broadcom/compiler/vir_register_allocate.c')
-rw-r--r--src/broadcom/compiler/vir_register_allocate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 9ebf2cd69b4..f39f0c2829b 100644
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -139,7 +139,7 @@ v3d_register_allocate(struct v3d_compile *c)
* result to a temp), nothing else can be stored in r3/r4 across
* it.
*/
- if (vir_writes_r3(inst)) {
+ if (vir_writes_r3(c->devinfo, inst)) {
for (int i = 0; i < c->num_temps; i++) {
if (c->temp_start[i] < ip &&
c->temp_end[i] > ip) {
@@ -149,7 +149,7 @@ v3d_register_allocate(struct v3d_compile *c)
}
}
}
- if (vir_writes_r4(inst)) {
+ if (vir_writes_r4(c->devinfo, inst)) {
for (int i = 0; i < c->num_temps; i++) {
if (c->temp_start[i] < ip &&
c->temp_end[i] > ip) {