diff options
| author | Eric Anholt <[email protected]> | 2017-12-11 12:52:27 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2019-01-14 15:40:55 -0800 |
| commit | 6281f26f064ada36b57d45feb68d8e7d783198c9 (patch) | |
| tree | d06588f36d6e2d273ae33cd9aaca640b3d027039 /src/broadcom/compiler/v3d_compiler.h | |
| parent | 5932c2f0b9b56e6eeee87baa7b0b493227850f69 (diff) | |
v3d: Add support for shader_image_load_store.
This is only exposed on V3D 4.1+, because we didn't have the TMU write
operations for images on 3.3 (To do GLES 3.1 there, you have to lower it
to SSBO load/stores, which is a problem to solve later).
Diffstat (limited to 'src/broadcom/compiler/v3d_compiler.h')
| -rw-r--r-- | src/broadcom/compiler/v3d_compiler.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h index a35a46c3316..a5f99d3dae8 100644 --- a/src/broadcom/compiler/v3d_compiler.h +++ b/src/broadcom/compiler/v3d_compiler.h @@ -230,6 +230,8 @@ enum quniform_contents { QUNIFORM_TMU_CONFIG_P0, QUNIFORM_TMU_CONFIG_P1, + QUNIFORM_IMAGE_TMU_CONFIG_P0, + QUNIFORM_TEXTURE_FIRST_LEVEL, QUNIFORM_TEXTURE_WIDTH, @@ -249,6 +251,12 @@ enum quniform_contents { /* Returns the size of the SSBO given by the data value. */ QUNIFORM_GET_BUFFER_SIZE, + /* Sizes (in pixels) of a shader image given by the data value. */ + QUNIFORM_IMAGE_WIDTH, + QUNIFORM_IMAGE_HEIGHT, + QUNIFORM_IMAGE_DEPTH, + QUNIFORM_IMAGE_ARRAY_SIZE, + QUNIFORM_ALPHA_REF, /** @@ -792,12 +800,15 @@ bool vir_opt_vpm(struct v3d_compile *c); void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c); void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c); void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c); +void v3d_nir_lower_image_load_store(nir_shader *s); void vir_lower_uniforms(struct v3d_compile *c); void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components); void v3d33_vir_vpm_write_setup(struct v3d_compile *c); void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr); void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr); +void v3d40_vir_emit_image_load_store(struct v3d_compile *c, + nir_intrinsic_instr *instr); void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers); uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c); @@ -805,6 +816,8 @@ void qpu_validate(struct v3d_compile *c); struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled); bool vir_init_reg_sets(struct v3d_compiler *compiler); +bool v3d_gl_format_is_return_32(GLenum format); + void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf); static inline bool |