diff options
| author | Eric Anholt <[email protected]> | 2018-01-04 15:35:28 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-01-12 21:54:33 -0800 |
| commit | 22a02f3e344d6bc47e3e30949a36d00a9eae84a9 (patch) | |
| tree | 632ed61f4bee7c932baf6383d256c4ec304994cd /src/broadcom/compiler/qpu_schedule.c | |
| parent | 55f8a01acae7c4171ccfef301e48dc3cc67f5836 (diff) | |
broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.
Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.
VPM loads also gain the ability to be reordered by packing the row into
the A argument. They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.
Diffstat (limited to 'src/broadcom/compiler/qpu_schedule.c')
| -rw-r--r-- | src/broadcom/compiler/qpu_schedule.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index 7fe46202636..cab117b523e 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -594,6 +594,9 @@ qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr) static bool qpu_accesses_peripheral(const struct v3d_qpu_instr *inst) { + if (v3d_qpu_uses_vpm(inst)) + return true; + if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { if (inst->alu.add.op != V3D_QPU_A_NOP && inst->alu.add.magic_write && @@ -601,9 +604,6 @@ qpu_accesses_peripheral(const struct v3d_qpu_instr *inst) return true; } - if (inst->alu.add.op == V3D_QPU_A_VPMSETUP) - return true; - if (inst->alu.mul.op != V3D_QPU_M_NOP && inst->alu.mul.magic_write && qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) { |