diff options
| author | Dave Airlie <[email protected]> | 2017-06-06 08:48:25 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-06-06 09:43:32 +1000 |
| commit | 98f27b9ccec3424ce5bd0ed3908c832e10605672 (patch) | |
| tree | 81bbc79b7a34997bd79238b76ef937eff1adff27 /src/amd | |
| parent | 77b8aa4d95678cf30210339d2afb75c7d1749f57 (diff) | |
radv: don't setup raster_config on gfx9.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 604a5e218ad..b848325c9b9 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -329,24 +329,28 @@ si_emit_config(struct radv_physical_device *physical_device, raster_config_1 = 0x00000000; break; default: - fprintf(stderr, - "radeonsi: Unknown GPU, using 0 for raster_config\n"); - raster_config = 0x00000000; - raster_config_1 = 0x00000000; + if (physical_device->rad_info.chip_class <= VI) { + fprintf(stderr, + "radeonsi: Unknown GPU, using 0 for raster_config\n"); + raster_config = 0x00000000; + raster_config_1 = 0x00000000; + } break; } /* Always use the default config when all backends are enabled * (or when we failed to determine the enabled backends). */ - if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { - radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, - raster_config); - if (physical_device->rad_info.chip_class >= CIK) - radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, - raster_config_1); - } else { - si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); + if (physical_device->rad_info.chip_class <= VI) { + if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { + radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, + raster_config); + if (physical_device->rad_info.chip_class >= CIK) + radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, + raster_config_1); + } else { + si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); + } } radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); |