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authorDave Airlie <[email protected]>2017-06-06 09:03:55 +1000
committerDave Airlie <[email protected]>2017-06-06 09:43:45 +1000
commit67655cb24fbd0d9dbacfb7c1059e21751b6c10eb (patch)
tree8c1854e4013d75140601d589c1a8c1a6250b5360 /src/amd
parentc2fbeb7ca057b3bee8c8cd0f7076af2b90d28111 (diff)
radv: add rb+ support for GFX9
This adds some rb+ support, as on GFX9 we have to disable it as per radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c7
-rw-r--r--src/amd/vulkan/radv_device.c6
-rw-r--r--src/amd/vulkan/radv_meta_clear.c5
-rw-r--r--src/amd/vulkan/radv_private.h3
-rw-r--r--src/amd/vulkan/si_cmd_buffer.c2
5 files changed, 22 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d078421182d..4fd0f4c00d1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -366,6 +366,13 @@ radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
8);
radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
+
+ if (cmd_buffer->device->physical_device->has_rbplus) {
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
+ radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
+ radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
+ radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
+ }
}
static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9d510ea59ea..d32c972ba29 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -304,6 +304,12 @@ radv_physical_device_init(struct radv_physical_device *device,
radv_get_device_uuid(drm_device, device->device_uuid);
+ if (device->rad_info.family == CHIP_STONEY ||
+ device->rad_info.chip_class >= GFX9) {
+ device->has_rbplus = true;
+ device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
+ }
+
return VK_SUCCESS;
fail:
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 66b77f406dc..f4cb78763f1 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -915,6 +915,11 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (clear_rect->layerCount != iview->image->info.array_size)
goto fail;
+ /* RB+ doesn't work with CMASK fast clear on Stoney. */
+ if (!iview->image->surface.dcc_size &&
+ cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
+ goto fail;
+
/* DCC */
ret = radv_format_pack_clear_color(iview->image->vk_format,
clear_color, &clear_value);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 6a6c1e2351a..ed80ba79e7f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -273,6 +273,9 @@ struct radv_physical_device {
int local_fd;
struct wsi_device wsi_device;
struct radv_extensions extensions;
+
+ bool has_rbplus; /* if RB+ register exist */
+ bool rbplus_allowed; /* if RB+ is allowed */
};
struct radv_instance {
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 3e0b8ee0200..397ea810084 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -452,7 +452,7 @@ si_emit_config(struct radv_physical_device *physical_device,
radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
}
- if (physical_device->rad_info.family == CHIP_STONEY)
+ if (physical_device->has_rbplus)
radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
if (physical_device->rad_info.chip_class >= GFX9) {