ac/surface: unify common legacy and gfx9 fmask fields

Reviewed-by: Nicolai Hähnle <[email protected]>

3 files changed, 19 insertions, 23 deletions

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b7423e5b520..22608c84351 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -853,9 +853,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 		if (r)
 			return r;
 
-		surf->u.legacy.fmask.size = fout.fmaskBytes;
-		surf->u.legacy.fmask.alignment = fout.baseAlign;
-		surf->u.legacy.fmask.tile_swizzle = 0;
+		surf->fmask_size = fout.fmaskBytes;
+		surf->fmask_alignment = fout.baseAlign;
+		surf->fmask_tile_swizzle = 0;
 
 		surf->u.legacy.fmask.slice_tile_max =
 			(fout.pitch * fout.height) / 64;
@@ -888,7 +888,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 
 			assert(xout.tileSwizzle <=
 			       u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
-			surf->u.legacy.fmask.tile_swizzle = xout.tileSwizzle;
+			surf->fmask_tile_swizzle = xout.tileSwizzle;
 		}
 	}
 
@@ -1178,8 +1178,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 
 			surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 			surf->u.gfx9.fmask.epitch = fout.pitch - 1;
-			surf->u.gfx9.fmask_size = fout.fmaskBytes;
-			surf->u.gfx9.fmask_alignment = fout.baseAlign;
+			surf->fmask_size = fout.fmaskBytes;
+			surf->fmask_alignment = fout.baseAlign;
 
 			/* Compute tile swizzle for the FMASK surface. */
 			if (config->info.fmask_surf_index &&
@@ -1205,8 +1205,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 					return ret;
 
 				assert(xout.pipeBankXor <=
-				       u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
-				surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
+				       u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
+				surf->fmask_tile_swizzle = xout.pipeBankXor;
 			}
 		}
 
@@ -1372,12 +1372,12 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	surf->num_dcc_levels = 0;
 	surf->surf_size = 0;
+	surf->fmask_size = 0;
 	surf->dcc_size = 0;
 	surf->htile_size = 0;
 	surf->htile_slice_size = 0;
 	surf->u.gfx9.surf_offset = 0;
 	surf->u.gfx9.stencil_offset = 0;
-	surf->u.gfx9.fmask_size = 0;
 	surf->u.gfx9.cmask_size = 0;
 
 	/* Calculate texture layout information. */
@@ -1472,7 +1472,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	/* Temporary workaround to prevent VM faults and hangs. */
 	if (info->family == CHIP_VEGA12)
-		surf->u.gfx9.fmask_size *= 8;
+		surf->fmask_size *= 8;
 
 	return 0;
 }
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index d0249684ad2..45fb8045e53 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -80,9 +80,6 @@ struct legacy_surf_level {
 };
 
 struct legacy_surf_fmask {
-    uint64_t size;
-    unsigned alignment;
-    unsigned tile_swizzle;
     unsigned slice_tile_max; /* max 4M */
     uint8_t tiling_index;    /* max 31 */
     uint8_t bankh;           /* max 8 */
@@ -153,13 +150,9 @@ struct gfx9_surf_layout {
     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 
     uint64_t                    stencil_offset; /* separate stencil */
-    uint64_t                    fmask_size;
     uint64_t                    cmask_size;
 
-    uint32_t                    fmask_alignment;
     uint32_t                    cmask_alignment;
-
-    uint8_t                     fmask_tile_swizzle;
 };
 
 struct radeon_surf {
@@ -199,8 +192,10 @@ struct radeon_surf {
      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
      */
     uint8_t                     tile_swizzle;
+    uint8_t                     fmask_tile_swizzle;
 
     uint64_t                    surf_size;
+    uint64_t                    fmask_size;
     /* DCC and HTILE are very small. */
     uint32_t                    dcc_size;
     uint32_t                    htile_size;
@@ -208,6 +203,7 @@ struct radeon_surf {
     uint32_t                    htile_slice_size;
 
     uint32_t                    surf_alignment;
+    uint32_t                    fmask_alignment;
     uint32_t                    dcc_alignment;
     uint32_t                    htile_alignment;
 
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ec99197fde9..5b13cf952b7 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -734,9 +734,9 @@ radv_image_get_fmask_info(struct radv_device *device,
 			  struct radv_fmask_info *out)
 {
 	if (device->physical_device->rad_info.chip_class >= GFX9) {
-		out->alignment = image->surface.u.gfx9.fmask_alignment;
-		out->size = image->surface.u.gfx9.fmask_size;
-		out->tile_swizzle = image->surface.u.gfx9.fmask_tile_swizzle;
+		out->alignment = image->surface.fmask_alignment;
+		out->size = image->surface.fmask_size;
+		out->tile_swizzle = image->surface.fmask_tile_swizzle;
 		return;
 	}
 
@@ -744,9 +744,9 @@ radv_image_get_fmask_info(struct radv_device *device,
 	out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
 	out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
 	out->bank_height = image->surface.u.legacy.fmask.bankh;
-	out->tile_swizzle = image->surface.u.legacy.fmask.tile_swizzle;
-	out->alignment = image->surface.u.legacy.fmask.alignment;
-	out->size = image->surface.u.legacy.fmask.size;
+	out->tile_swizzle = image->surface.fmask_tile_swizzle;
+	out->alignment = image->surface.fmask_alignment;
+	out->size = image->surface.fmask_size;
 
 	assert(!out->tile_swizzle || !image->shareable);
 }