diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-07-14 14:28:20 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2018-07-19 02:37:54 +0200 |
| commit | 760211b77c7aabc9264542f18e42f366b0fef33f (patch) | |
| tree | 5cd4d9ae7b4b1d99f3376d208123be21eec2c587 /src/amd | |
| parent | c0144e915a8f8ece6f6019ff626220dd70c57967 (diff) | |
radv: Fix number of samples used for binning.
Used the wrong register ...
CC: <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1f01d2ff4d6..4c794d9515d 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2443,7 +2443,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr pipeline->device->physical_device->rad_info.max_se); unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se); - unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1); + unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config); unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa); unsigned effective_samples = total_samples; unsigned color_bytes_per_pixel = 0; |