ac: add radeon_info::num_rings and move ring_type to amd_family.h

Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>

6 files changed, 23 insertions, 20 deletions

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 23dcb190a3f..c40427987f7 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -500,8 +500,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 	assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
 
 	info->has_graphics = gfx.available_rings > 0;
-	info->num_sdma_rings = util_bitcount(dma.available_rings);
-	info->num_compute_rings = util_bitcount(compute.available_rings);
+	info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
+	info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
 
 	/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
 	 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
@@ -708,8 +708,8 @@ void ac_print_gpu_info(struct radeon_info *info)
 
 	printf("Features:\n");
 	printf("    has_graphics = %i\n", info->has_graphics);
-	printf("    num_compute_rings = %u\n", info->num_compute_rings);
-	printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
+	printf("    num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
+	printf("    num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
 	printf("    has_clear_state = %u\n", info->has_clear_state);
 	printf("    has_distributed_tess = %u\n", info->has_distributed_tess);
 	printf("    has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cffa0b7b222..412332ea70d 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -57,8 +57,7 @@ struct radeon_info {
 
 	/* Features. */
 	bool                        has_graphics; /* false if the chip is compute-only */
-	uint32_t                    num_compute_rings;
-	uint32_t                    num_sdma_rings;
+	uint32_t                    num_rings[NUM_RING_TYPES];
 	bool                        has_clear_state;
 	bool                        has_distributed_tess;
 	bool                        has_dcc_constant_encode;
diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 2386eecb5d4..ffcc1bd9240 100644
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -121,4 +121,17 @@ enum chip_class {
     GFX10,
 };
 
+enum ring_type {
+    RING_GFX = 0,
+    RING_COMPUTE,
+    RING_DMA,
+    RING_UVD,
+    RING_VCE,
+    RING_UVD_ENC,
+    RING_VCN_DEC,
+    RING_VCN_ENC,
+    RING_VCN_JPEG,
+    NUM_RING_TYPES,
+};
+
 #endif
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 226eee0246a..15cc163c140 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1701,7 +1701,7 @@ static void radv_get_physical_device_queue_family_properties(
 {
 	int num_queue_families = 1;
 	int idx;
-	if (pdevice->rad_info.num_compute_rings > 0 &&
+	if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
 	    !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
 		num_queue_families++;
 
@@ -1727,14 +1727,14 @@ static void radv_get_physical_device_queue_family_properties(
 		idx++;
 	}
 
-	if (pdevice->rad_info.num_compute_rings > 0 &&
+	if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
 	    !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
 		if (*pCount > idx) {
 			*pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
 				.queueFlags = VK_QUEUE_COMPUTE_BIT |
 				              VK_QUEUE_TRANSFER_BIT |
 				              VK_QUEUE_SPARSE_BINDING_BIT,
-				.queueCount = pdevice->rad_info.num_compute_rings,
+				.queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
 				.timestampValidBits = 64,
 				.minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
 			};
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index ba464dea884..339578d1a33 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -69,15 +69,6 @@ enum radeon_bo_usage { /* bitfield */
 	RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
 };
 
-enum ring_type {
-	RING_GFX = 0,
-	RING_COMPUTE,
-	RING_DMA,
-	RING_UVD,
-	RING_VCE,
-	RING_LAST,
-};
-
 enum radeon_ctx_priority {
 	RADEON_CTX_PRIORITY_INVALID = -1,
 	RADEON_CTX_PRIORITY_LOW = 0,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index 934caf17d25..a77508faf94 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -62,8 +62,8 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
 		return false;
 	}
 
-	ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
-	ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
+	ws->info.num_rings[RING_DMA] = MIN2(ws->info.num_rings[RING_DMA], MAX_RINGS_PER_TYPE);
+	ws->info.num_rings[RING_COMPUTE] = MIN2(ws->info.num_rings[RING_COMPUTE], MAX_RINGS_PER_TYPE);
 
 	ws->use_ib_bos = ws->info.chip_class >= GFX7;
 	return true;