summaryrefslogtreecommitdiffstats
path: root/src/amd
diff options
context:
space:
mode:
authorSamuel Pitoiset <[email protected]>2019-07-01 16:30:58 +0200
committerSamuel Pitoiset <[email protected]>2019-07-02 09:37:51 +0200
commite47c68b7b0566150d85e84c1a9c0fa268d7278c8 (patch)
treecd011a838acfdee0ec5ef79757e782a0c1aa276a /src/amd
parentf772fe6a1173216806383d39c938ef8181a84991 (diff)
radv: merge radv_dcc_clear_level() into radv_clear_dcc()
This will help for clearing DCC arrays because we need to know the subresource range. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_meta_clear.c52
1 files changed, 22 insertions, 30 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index b0b17f4f7b3..e5181daf0f2 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1367,34 +1367,6 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
-static uint32_t
-radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
- const struct radv_image *image,
- uint32_t level, uint32_t value)
-{
- uint64_t offset = image->offset + image->dcc_offset;
- uint32_t size;
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
- /* Mipmap levels aren't implemented. */
- assert(level == 0);
- size = image->planes[0].surface.dcc_size;
- } else {
- const struct legacy_surf_level *surf_level =
- &image->planes[0].surface.u.legacy.level[level];
-
- /* If dcc_fast_clear_size is 0 (which might happens for
- * mipmaps) the fill buffer operation below is a no-op. This
- * can only happen during initialization as the fast clear path
- * fallbacks to slow clears if one level can't be fast cleared.
- */
- offset += surf_level->dcc_offset;
- size = surf_level->dcc_fast_clear_size;
- }
-
- return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
-}
-
uint32_t
radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
@@ -1407,10 +1379,30 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
radv_update_dcc_metadata(cmd_buffer, image, range, true);
for (uint32_t l = 0; l < level_count; l++) {
+ uint64_t offset = image->offset + image->dcc_offset;
uint32_t level = range->baseMipLevel + l;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* Mipmap levels aren't implemented. */
+ assert(level == 0);
+ size = image->planes[0].surface.dcc_size;
+ } else {
+ const struct legacy_surf_level *surf_level =
+ &image->planes[0].surface.u.legacy.level[level];
+
+ /* If dcc_fast_clear_size is 0 (which might happens for
+ * mipmaps) the fill buffer operation below is a no-op.
+ * This can only happen during initialization as the
+ * fast clear path fallbacks to slow clears if one
+ * level can't be fast cleared.
+ */
+ offset += surf_level->dcc_offset;
+ size = surf_level->dcc_fast_clear_size;
+ }
- flush_bits |= radv_dcc_clear_level(cmd_buffer, image,
- level, value);
+ flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
+ size, value);
}
return flush_bits;