diff options
| author | Rhys Perry <[email protected]> | 2020-03-16 13:47:55 +0000 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-16 19:34:32 +0000 |
| commit | ded7a8bb4625b28add06f8550526f2169045e87c (patch) | |
| tree | d1883e0a620f3be79207c7cff15ed6aa9a70712b /src/amd | |
| parent | ee9e0d1ecae307fa48200d2604d3114070253299 (diff) | |
aco: fix instruction encoding for LS VGPR init bug workaround
Fixes: a952bf3946 ('aco: Fix LS VGPR init bug on affected hardware.')
Signed-off-by: Rhys Perry <[email protected]>
Reviewed-By: Timur Kristóf <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 195c57950c5..ff39ad854cd 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9501,15 +9501,15 @@ void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm) /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */ - Temp instance_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1), + Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->ac.instance_id), get_arg(ctx, ctx->args->rel_auto_id), ls_has_nonzero_hs_threads); - Temp rel_auto_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1), + Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->rel_auto_id), get_arg(ctx, ctx->args->ac.tcs_rel_ids), ls_has_nonzero_hs_threads); - Temp vertex_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1), + Temp vertex_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->ac.vertex_id), get_arg(ctx, ctx->args->ac.tcs_patch_id), ls_has_nonzero_hs_threads); |